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Fix part select issues in LATCH warning. (verilator#2948) (verilator#…
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#!/usr/bin/env perl | ||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you | ||
# can redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
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scenarios(vlt => 1); | ||
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lint( | ||
); | ||
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ok(1); | ||
1; |
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// DESCRIPTION: Verilator: Verilog Test module for Issue#2938 | ||
// | ||
// This file ONLY is placed into the Public Domain, for any use, | ||
// without warranty, 2021 by Julien Margetts (Originally provided by YanJiun) | ||
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module test ( | ||
input [2:0] a, | ||
input [3:0] c, | ||
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output reg [7:0] b | ||
); | ||
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integer i; | ||
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always @ (*) | ||
begin | ||
case(a) | ||
{3'b000}: b = 8'd1; | ||
{3'b001}: | ||
for(i=0;i<4;i=i+1) b[i*2+:2] = 2'(c[i]); | ||
{3'b010}: b = 8'd3; | ||
{3'b011}: b = 8'd4; | ||
default : b = 0; | ||
endcase | ||
end | ||
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endmodule |