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lahaina.dtsi
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#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-lahaina.h>
#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
#include <dt-bindings/clock/qcom,gcc-lahaina.h>
#include <dt-bindings/clock/qcom,gpucc-lahaina.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-lahaina.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,lahaina.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/gpio/gpio.h>
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
opp-supported-hw = <ddrtype>;}
#define DDR_TYPE_LPDDR4X 7
#define DDR_TYPE_LPDDR5 8
/ {
model = "Qualcomm Technologies, Inc. Lahaina";
compatible = "qcom,lahaina";
qcom,msm-id = <415 0x10000>, <456 0x10000>, <501 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &qupv3_se3_2uart;
hsuart0 = &qupv3_se18_4uart;
pci-domain0 = &pcie0; /* PCIe0 domain */
pci-domain1 = &pcie1; /* PCIe1 domain */
swr0 = &swr0;
swr1 = &swr1;
swr2 = &swr2;
usb0 = &usb0;
usb1 = &usb1;
};
firmware: firmware {};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <515>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
capacity-dmips-mhz = <2048>;
dynamic-power-coefficient = <845>;
cpu-idle-states = <&GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
};
cluster2 {
core0 {
cpu = <&CPU7>;
};
};
};
};
soc: soc { };
};
&firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok";
};
};
};
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_region@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: reserved-memory@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
cdsp_secure_heap: cdsp_secure_heap@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0x4600000>;
};
pil_camera_mem: pil_camera_region@85200000 {
no-map;
reg = <0x0 0x85200000 0x0 0x500000>;
};
pil_video_mem: pil_video_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x500000>;
};
pil_cvp_mem: pil_cvp_region@85c00000 {
no-map;
reg = <0x0 0x85c00000 0x0 0x500000>;
};
pil_adsp_mem: pil_adsp_region@86100000 {
no-map;
reg = <0x0 0x86100000 0x0 0x2100000>;
};
pil_slpi_mem: pil_slpi_region@88200000 {
no-map;
reg = <0x0 0x88200000 0x0 0x1500000>;
};
pil_cdsp_mem: pil_cdsp_region@89700000 {
no-map;
//#ifndef OPLUS_FEATURE_SENSOR_DRIVER
//reg = <0x0 0x89700000 0x0 0x1e00000>;
//#else
reg = <0x0 0x89700000 0x0 0x1400000>;
//#endif
};
pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 {
no-map;
reg = <0x0 0x8b500000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 {
no-map;
reg = <0x0 0x8b510000 0x0 0xa000>;
};
pil_gpu_mem: pil_gpu_region@8b51a000 {
no-map;
reg = <0x0 0x8b51a000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@8b600000 {
no-map;
reg = <0x0 0x8b600000 0x0 0x100000>;
};
pil_modem_mem: modem_region@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0x10000000>;
};
hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 {
no-map;
//#ifdef OPLUS_FEATURE_BOOT_SECURITY
/* 2020/12/16, delete for not use TVM TUI */
//reg = <0x0 0xd0000000 0x0 0x800000>;
//#endif /* OPLUS_FEATURE_BOOT_SECURITY */
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
//#ifdef OPLUS_FEATURE_BOOT_SECURITY
/* 2020/12/16, delete for not use TVM TUI */
//reg = <0x0 0xd0800000 0x0 0x76f7000>;
//#endif /* OPLUS_FEATURE_BOOT_SECURITY */
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
removed_mem: removed_region@d8800000 {
no-map;
reg = <0x0 0xd8800000 0x0 0x6800000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA400000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
#ifndef OPLUS_BUG_STABILITY
#size = <0x0 0x1400000>;
#else
size = <0x0 0x1E00000>;
#endif /* OPLUS_BUG_STABILITY */
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x3000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
/*
* Demura memory regions are to be commented out if
* feature not in use.
*/
demura_memory_0: demura_region_0 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 0";
};
demura_memory_1: demura_region_1 {
reg = <0x0 0x0 0x0 0x0>;
label = "demura hfc region 1";
};
dfps_data_memory: dfps_data_region {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_region";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
system_pm {
compatible = "qcom,system-pm";
};
clock_rpmh: qcom,rpmhclk {
compatible = "qcom,lahaina-rpmh-clk";
#clock-cells = <1>;
};
};
slim_aud: slim@3ac0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0x3ac0000 0x2c000>,
<0x3a84000 0x22000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x350>;
iommus = <&apps_smmu 0x1826 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
/* Slimbus Slave DT for QCA6490 */
btfmslim_codec: qca6490 {
compatible = "qcom,btfmslim_slave";
elemental-addr = [00 01 21 02 17 02];
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
qcom,btfm-slim-ifd-elemental-addr = [00 00 21 02 17 02];
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1112000 0x6000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
link_list1 {
qcom,curr-link-list = <6>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_WRITE 0x18080010 0x1 0>,
<DCC_READ 0x00144018 1 0>,
<DCC_WRITE 0x00144018 0x1 0>,
<DCC_READ 0x00144018 1 0>,
<DCC_READ 0x091a9020 1 0>,
<DCC_READ_WRITE 0x5 0x1 0>,
<DCC_READ 0x09102008 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09142008 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09102408 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09142408 1 0>,
<DCC_READ_WRITE 0x2 0x2 0>,
<DCC_READ 0x09103808 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09103810 1 0>,
<DCC_READ 0x09103814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103888 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09103890 1 0>,
<DCC_READ 0x09103894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143808 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09143810 1 0>,
<DCC_READ 0x09143814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143888 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09143890 1 0>,
<DCC_READ 0x09143894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182808 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x09182810 1 0>,
<DCC_READ 0x09182814 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182888 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x09182890 1 0>,
<DCC_READ 0x09182894 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103008 1 0>,
<DCC_READ 0x0910300c 1 0>,
<DCC_WRITE 0x09103028 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09103010 1 0>,
<DCC_READ 0x09103014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09103408 1 0>,
<DCC_READ 0x0910340c 1 0>,
<DCC_WRITE 0x09103428 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09103410 1 0>,
<DCC_READ 0x09103414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143008 1 0>,
<DCC_READ 0x0914300c 1 0>,
<DCC_WRITE 0x09143028 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09143010 1 0>,
<DCC_READ 0x09143014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09143408 1 0>,
<DCC_READ 0x0914340c 1 0>,
<DCC_WRITE 0x09143428 0x00000001 1>,
<DCC_LOOP 41 0 0>,
<DCC_READ 0x09143410 1 0>,
<DCC_READ 0x09143414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182008 1 0>,
<DCC_READ 0x0918200c 1 0>,
<DCC_WRITE 0x09182028 0x00000001 1>,
<DCC_LOOP 11 0 0>,
<DCC_READ 0x09182010 1 0>,
<DCC_READ 0x09182014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x09182408 1 0>,
<DCC_READ 0x0918240c 1 0>,
<DCC_WRITE 0x09182428 0x00000001 1>,
<DCC_LOOP 11 0 0>,
<DCC_READ 0x09182410 1 0>,
<DCC_READ 0x09182414 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x18000024 1 0>,
<DCC_READ 0x18000040 4 0>,
<DCC_READ 0x18010024 1 0>,
<DCC_READ 0x18010040 4 0>,
<DCC_READ 0x18020024 1 0>,
<DCC_READ 0x18020040 4 0>,
<DCC_READ 0x18030024 1 0>,
<DCC_READ 0x18030040 4 0>,
<DCC_READ 0x18040024 1 0>,
<DCC_READ 0x18040040 4 0>,
<DCC_READ 0x18050024 1 0>,
<DCC_READ 0x18050040 4 0>,
<DCC_READ 0x18060024 1 0>,
<DCC_READ 0x18060040 4 0>,
<DCC_READ 0x18070024 1 0>,
<DCC_READ 0x18070040 4 0>,
<DCC_READ 0x18080024 1 0>,
<DCC_READ 0x18080040 3 0>,
<DCC_READ 0x180800f8 1 0>,
<DCC_READ 0x18080104 1 0>,
<DCC_READ 0x1808011c 1 0>,
<DCC_READ 0x18080128 1 0>,
<DCC_READ 0x18080168 1 0>,
<DCC_READ 0x18080198 1 0>,
<DCC_READ 0x9050078 1 0>,
<DCC_READ 0x9050110 8 0>,
<DCC_READ 0x9080058 2 0>,
<DCC_READ 0x90800c8 1 0>,
<DCC_READ 0x90800d4 1 0>,
<DCC_READ 0x90800e0 1 0>,
<DCC_READ 0x90800ec 1 0>,
<DCC_READ 0x90800f8 1 0>,
<DCC_READ 0x9084030 1 0>,
<DCC_READ 0x9084038 2 0>,
<DCC_READ 0x90840e4 1 0>,
<DCC_READ 0x90840f4 1 0>,
<DCC_READ 0x9084104 2 0>,
<DCC_READ 0x9084194 1 0>,
<DCC_READ 0x9084804 1 0>,
<DCC_READ 0x908480c 1 0>,
<DCC_READ 0x9084844 1 0>,
<DCC_READ 0x9084850 2 0>,
<DCC_READ 0x9084860 3 0>,
<DCC_READ 0x9084888 1 0>,
<DCC_READ 0x908488c 1 0>,
<DCC_READ 0x9084900 1 0>,
<DCC_READ 0x908409c 1 0>,
<DCC_READ 0x90840a0 1 0>,
<DCC_READ 0x908426c 1 0>,
<DCC_READ 0x908439c 1 0>,
<DCC_READ 0x9085124 1 0>,
<DCC_READ 0x90ba280 1 0>,
<DCC_READ 0x90ba288 7 0>,
<DCC_READ 0x9258610 4 0>,
<DCC_READ 0x92d8610 4 0>,
<DCC_READ 0x9358610 4 0>,
<DCC_READ 0x93d8610 4 0>,
<DCC_READ 0x9220344 8 0>,
<DCC_READ 0x9220370 6 0>,
<DCC_READ 0x9220480 1 0>,
<DCC_READ 0x9222400 1 0>,
<DCC_READ 0x922240c 1 0>,
<DCC_READ 0x9223214 2 0>,
<DCC_READ 0x9223220 3 0>,
<DCC_READ 0x9223308 1 0>,
<DCC_READ 0x9223318 1 0>,
<DCC_READ 0x9232100 1 0>,
<DCC_READ 0x9236040 6 0>,
<DCC_READ 0x92360b0 1 0>,
<DCC_READ 0x923a004 4 0>,
<DCC_READ 0x923e030 2 0>,
<DCC_READ 0x9241000 1 0>,
<DCC_READ 0x9242028 1 0>,
<DCC_READ 0x9242044 3 0>,
<DCC_READ 0x9242070 1 0>,
<DCC_READ 0x9248030 1 0>,
<DCC_READ 0x9248048 8 0>,
<DCC_READ 0x92a0344 8 0>,
<DCC_READ 0x92a0370 6 0>,
<DCC_READ 0x92a0480 1 0>,
<DCC_READ 0x92a2400 1 0>,
<DCC_READ 0x92a240c 1 0>,
<DCC_READ 0x92a3214 2 0>,
<DCC_READ 0x92a3220 3 0>,
<DCC_READ 0x92a3308 1 0>,
<DCC_READ 0x92a3318 1 0>,
<DCC_READ 0x92b2100 1 0>,
<DCC_READ 0x92b6040 6 0>,
<DCC_READ 0x92b60b0 1 0>,
<DCC_READ 0x92ba004 4 0>,
<DCC_READ 0x92be030 2 0>,
<DCC_READ 0x92c1000 1 0>,
<DCC_READ 0x92c2028 1 0>,
<DCC_READ 0x92c2044 3 0>,
<DCC_READ 0x92c2070 1 0>,
<DCC_READ 0x92c8030 1 0>,
<DCC_READ 0x92c8048 8 0>,
<DCC_READ 0x9320344 8 0>,
<DCC_READ 0x9320370 6 0>,
<DCC_READ 0x9320480 1 0>,
<DCC_READ 0x9322400 1 0>,
<DCC_READ 0x932240c 1 0>,
<DCC_READ 0x9323214 2 0>,
<DCC_READ 0x9323220 3 0>,
<DCC_READ 0x9323308 1 0>,
<DCC_READ 0x9323318 1 0>,
<DCC_READ 0x9332100 1 0>,
<DCC_READ 0x9336040 6 0>,
<DCC_READ 0x93360b0 1 0>,
<DCC_READ 0x933a004 4 0>,
<DCC_READ 0x933e030 2 0>,
<DCC_READ 0x9341000 1 0>,
<DCC_READ 0x9342028 1 0>,
<DCC_READ 0x9342044 3 0>,
<DCC_READ 0x9342070 1 0>,
<DCC_READ 0x9348030 1 0>,
<DCC_READ 0x9348048 8 0>,
<DCC_READ 0x93a0344 8 0>,
<DCC_READ 0x93a0370 6 0>,
<DCC_READ 0x93a0480 1 0>,
<DCC_READ 0x93a2400 1 0>,
<DCC_READ 0x93a240c 1 0>,
<DCC_READ 0x93a3214 2 0>,
<DCC_READ 0x93a3220 3 0>,
<DCC_READ 0x93a3308 1 0>,
<DCC_READ 0x93a3318 1 0>,
<DCC_READ 0x93b2100 1 0>,
<DCC_READ 0x93b6040 6 0>,
<DCC_READ 0x93b60b0 1 0>,
<DCC_READ 0x93ba004 4 0>,
<DCC_READ 0x93be030 2 0>,
<DCC_READ 0x93c1000 1 0>,
<DCC_READ 0x93c2028 1 0>,
<DCC_READ 0x93c2044 3 0>,
<DCC_READ 0x93c2070 1 0>,
<DCC_READ 0x93c8030 1 0>,
<DCC_READ 0x93c8048 8 0>,
<DCC_READ 0x9270080 1 0>,
<DCC_READ 0x9270310 1 0>,
<DCC_READ 0x9270400 1 0>,
<DCC_READ 0x9270410 6 0>,
<DCC_READ 0x9270430 1 0>,
<DCC_READ 0x9270440 1 0>,
<DCC_READ 0x9270448 1 0>,
<DCC_READ 0x92704a0 1 0>,
<DCC_READ 0x92704b0 1 0>,
<DCC_READ 0x92704b8 2 0>,
<DCC_READ 0x92704d0 2 0>,
<DCC_READ 0x9271400 1 0>,
<DCC_READ 0x9271408 1 0>,
<DCC_READ 0x927341c 1 0>,
<DCC_READ 0x92753b0 1 0>,
<DCC_READ 0x9275804 1 0>,
<DCC_READ 0x9275c1c 1 0>,
<DCC_READ 0x9275c2c 1 0>,
<DCC_READ 0x9275c38 1 0>,
<DCC_READ 0x9276418 2 0>,
<DCC_READ 0x9279100 1 0>,
<DCC_READ 0x9279110 1 0>,
<DCC_READ 0x9279120 1 0>,
<DCC_READ 0x9279180 2 0>,
<DCC_READ 0x92f0080 1 0>,
<DCC_READ 0x92f0310 1 0>,
<DCC_READ 0x92f0400 1 0>,
<DCC_READ 0x92f0410 6 0>,
<DCC_READ 0x92f0430 1 0>,
<DCC_READ 0x92f0440 1 0>,
<DCC_READ 0x92f0448 1 0>,
<DCC_READ 0x92f04a0 1 0>,
<DCC_READ 0x92f04b0 1 0>,