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alpha: Introduce UMUL_HIGHPART rtx_code [PR113720]
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umuldi3_highpart expander does:

   if (REG_P (operands[2]))
     operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);

on register_operand predicate, which also allows SUBREG RTX. So,
subregs were emitted without ZERO_EXTEND RTX.

But nowadays we have UMUL_HIGHPART that allows us to fix this
issue while also simplifying the instruction RTX.

    PR target/113720

gcc/ChangeLog:

    * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
    (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
    simplify insn RTX using UMUL_HIGHPART rtx_code.
    (*umuldi3_highpart_const): Remove.

Tested by building a cross-compiler to alpha-linux-gnu.

Uros.
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ubizjak authored and ouuleilei-bot committed Mar 3, 2024
1 parent c2d62cd commit 55b8efc
Showing 1 changed file with 3 additions and 34 deletions.
37 changes: 3 additions & 34 deletions gcc/config/alpha/alpha.md
Original file line number Diff line number Diff line change
Expand Up @@ -683,41 +683,10 @@
[(set_attr "type" "imul")
(set_attr "opsize" "<mode>")])

(define_expand "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand")
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI
(match_operand:DI 1 "register_operand"))
(match_operand:DI 2 "reg_or_8bit_operand"))
(const_int 64))))]
""
{
if (REG_P (operands[2]))
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
})

(define_insn "*umuldi3_highpart_reg"
[(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI
(match_operand:DI 1 "register_operand" "r"))
(zero_extend:TI
(match_operand:DI 2 "register_operand" "r")))
(const_int 64))))]
""
"umulh %1,%2,%0"
[(set_attr "type" "imul")
(set_attr "opsize" "udi")])

(define_insn "*umuldi3_highpart_const"
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
(match_operand:TI 2 "cint8_operand" "I"))
(const_int 64))))]
(umul_highpart:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
(match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
""
"umulh %1,%2,%0"
[(set_attr "type" "imul")
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