Icicle Kit Reference Design Release 2021.04

Changes since last release

This release introduces several updates and additions to the reference design and MSS configuration:

Added support for Libero 2021.1
Core names cleaned up to reflect their function instead of the core itself
Updated cores to the latest versions
LSRAM usage of the design was reduced
Added a PF CCC connected to the DRI generating clocks which output to the RPI I/O
Clock and reset generation was consolidated into a single SmartDesign called “Clocks and Resets”
Enabled FIC2 and connected it to the 125MHz clock
Added path length check for Windows and Libero version check for Linux and Windows
Updated MSS configurator save files and provided XML to 2021.1 format
Changed MMC voltage level to 1.8V
Enabled QSPI and connected to MikroBus
Enabled MMUART4 and connected to MikroBus
Enabled I2C0 and connected to MikroBus
Enabled SPI0 and connected to RPI I/O
L2 cache configuration was updated to allocate:
- 8 ways to cache
- 4 ways to L2 LIM
- 4 ways to scratchpad
DDR memory partition was updated to allocate:
- 768MB of cached DDR to 0x8000_0000
- 256MB of non-cached DDR to 0xC000_0000
- 1GB of cached DDR to 0x10_0000_0000

The MMC voltage level change requires jumpers 34 and 43 of the Icicle Kit to be changed from the 1 & 2 position to the 2 & 3 position.

To fully use the changes in this design ensure you update your embedded software project to use the latest version of MSS configuration description XML file.