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2021.08
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@Cyril-Jean Cyril-Jean released this 06 Aug 15:14
· 296 commits to master since this release
2021.08
0de8bad

Icicle Kit Reference Design 2021.08

Libero version

This release is intended for use with Libero 2021.1.

Pre-built programming files

The Icicle-Kit-2021.08.zip release asset file contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services 0.99.23. This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Changes since the last release

Support for argument based design generation was added. This allows reconfiguration of the design by passing an argument at generation time. Supported targets include:

  • I2C_LOOPBACK: routes both I2C peripherals to I/Os so they can be looped back
  • SPI_LOOPBACK: routes both SPI peripherals to I/Os so they can be looped back
  • BFM_SIMULATION: generates a SmartDesign test bench which can be used for BFM simulations

Arguments have been added to run the flow and also update the HSS:

  • SYNTHESIZE: runs synthesis after generating a design
  • PLACEROUTE: runs synthesis and place and route after generating a design
  • VERIFYTIMING: runs required steps and timing verification after generating a design
  • GENERATE_BITSTREAM: runs required steps and generates files to generate a programming bitstream after generating a design
  • PROGRAM: runs the required steps and programs a connected device after generating a design
  • EXPORT_FPE: runs the required steps and exports a FlashPro Express programming file after generating a design
  • HSS_UPDATE: runs the required steps and downloads and adds the associated HSS release hex file to the Libero project after generating a design

Updated CAN clock frequency in the MSS configuration to 8MHz.

Updated provided XML with the updated CAN clock configuration and added XML for I2C loop back and SPI loop back.

Updated the core voltage setting in the project to 1.05v which requires J45 to be set to the 1.05v position for accurate timing data.

Renamed *_MASTER cores to *_INITIATOR.

Updated the configuration of FIC0_INITIATOR to accommodate PCIe changes by removing PCIe access at address 0x7000_0000 and allowing access only through address 0x20_0000_0000.

Updated the configuration of PCIE_INITIATOR to accommodate PCIe changes to allow access to the 38 bit addressable DDR.

Updated the base design to accommodate PCIe changes by adding gates to act as an address shim and offset addresses from PCIe to 0x10_xxxx_xxxx.

Added a fabric PWM core to FIC3 at address 0x4100_0000 and connected the output to the Mikrobus PWM pin:

  • The PWM output is OR'd with the QSPI_DATA3 output
  • Note: the PWM core and QSPI peripheral cannot be used simultaneously

Removed unnecessary project saves, design hierarchy builds and tool calls to improve stability and run time.

Moved constraints to the script_support folder.

Resolved warnings generated after running the scripts.

Updated readme and block diagram.

Assets 3
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