riscv: Add UBI and UBIFS support

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
polarfire-soc · Aug 31, 2022 · b95e3aa · b95e3aa
1 parent d4252b9
commit b95e3aa
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Showing 3 changed files with 101 additions and 1 deletion.
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Microchip Technology Inc.
+ */
+
+#ifndef _RISCV_ATOMIC_H
+#define _RISCV_ATOMIC_H
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
@@ -32,7 +32,7 @@
 /*
  * Function prototypes to keep gcc -Wall happy.
  */
-static inline void __set_bit(int nr, void *addr)
+static inline void set_bit(int nr, void *addr)
 {
 	int *a = (int *)addr;
 	int mask;
@@ -42,6 +42,15 @@ static inline void __set_bit(int nr, void *addr)
 	*a |= mask;
 }
 
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
 #define PLATFORM__SET_BIT
 
 static inline void __clear_bit(int nr, void *addr)
@@ -54,6 +63,16 @@ static inline void __clear_bit(int nr, void *addr)
 	*a &= ~mask;
 }
 
+static inline void clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a &= ~mask;
+}
+
 #define PLATFORM__CLEAR_BIT
 
 static inline void __change_bit(int nr, void *addr)
@@ -66,6 +85,26 @@ static inline void __change_bit(int nr, void *addr)
 	*ADDR ^= mask;
 }
 
+static inline void change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+static inline int test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
 static inline int __test_and_set_bit(int nr, void *addr)
 {
 	int mask, retval;
@@ -77,7 +116,17 @@ static inline int __test_and_set_bit(int nr, void *addr)
 	*a |= mask;
 	return retval;
 }
+static inline int test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
 
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
 static inline int __test_and_clear_bit(int nr, void *addr)
 {
 	int mask, retval;
@@ -89,6 +138,17 @@ static inline int __test_and_clear_bit(int nr, void *addr)
 	*a &= ~mask;
 	return retval;
 }
+static inline int test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
 
 static inline int __test_and_change_bit(int nr, void *addr)
 {

diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
@@ -14,4 +14,32 @@
  *
  */
 
+static inline void local_irq_save(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_enable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_disable(void)
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_save_flags(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
+static inline void local_irq_restore(
+	unsigned long flags __attribute__((unused)))
+{
+	__asm__ __volatile__ ("" : : : "memory");
+}
+
 #endif	/* __ASM_RISCV_SYSTEM_H */