How can I use it?

[superblaubeere27]

I had the same idea and found this repo. How can I synthesize verilog to redstone?

[porglezomp]

This repo is pretty incomplete, it has most of the synthesis components but no place-and-route capabilities so you'll have to build circuits it synthesizes by hand. genlib.py will produce a liberty file for logic cells that are easily built with redstone (they're mostly all a row of blocks with torches on the side or on top), and then the examples directory shows how you can use yosys to synthesize with that cell library. After that, you have to put the cells in the world yourself.

For a useful fully automated component, you can use the romgen script to automatically generate a ROM with some given contents, and you can use the "litho" program in mc-mask to place those collections of blocks into a server.

[superblaubeere27]

Oh ok, I thouht you also figured out how to use nextpnr to place and route the cells. The PNR phase is the hardest to do by far :/

[porglezomp]

I'm not sure nextpnr is actually the appropriate tool, since it's designed for FPGA layouts, which means they have fixed cell positions and fixed wire layouts. You could design an FPGA style grid and fill that in with a nextpnr template, but it would probably be inefficient use of space because you could also be freely placing cells and wires, and would require all that difficult grid layout design up front.

[superblaubeere27]

I tried to create a program that automatically routes a circuit. Every approach I tried till now failed, but I still have a few left to try. Thanks for your time!