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Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog

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Instructions.txt

Instructions.txt

 
 

OddPipe.sv

OddPipe.sv

 
 

OddPipe.sv.bak

OddPipe.sv.bak

 
 

README.md

README.md

 
 

decode.sv

decode.sv

 
 

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even_pipe.sv

even_pipe.sv

 
 

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fetch.sv

fetch.sv

 
 

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issue.sv

issue.sv

 
 

issue.sv.bak

issue.sv.bak

 
 

register_file.sv

register_file.sv

 
 

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SonyCellSPU

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Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog

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