Fix table.

preusser · Oct 24, 2017 · c8df61d · c8df61d
1 parent fc37c28
commit c8df61d
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/README.md b/README.md
@@ -122,12 +122,13 @@ The full [computation log is available](https://palios.inf.tu-dresden.de/q27stat
    Count | Board | Family | Device | Solvers | Clock | SE
    ------|-------|--------|--------|---------|-------|-----
    1x    | VC707 | Xilinx Virtex-7      | XC7VX485T-2     | 325 | 250.0 MHz | 812
-         |(VC707)|(Xilinx Virtex-7)     |(XC7VX485T-2)    |(360)|(248.0 MHz)|(892)
+   (1x)  |(VC707)|(Xilinx Virtex-7)     |(XC7VX485T-2)    |(360)|(248.0 MHz)|(892)
    1x    | KC705 | Xilinx Kintex-7      | XC7K325T-2      | 250 | 284.4 MHz | 711
    1x    | ML605 | Xilinx Virtex-6      | XC6VLX240T-1    | 127 | 171.4 MHz | 217
    2x    | DE4   | Altera Stratix IV GX | EP4SGX230KF40C2 | 125 | 250.0 MHz | 312
    4x    | DNK7_F5_PCIe| Xilinx Kintex-7| 5x XC7K325T     | 5x240 | 220.0 MHz |2640
    4x    | SDRC4 | Xilinx Virtex-4      | 4x XC4VLX160-10 | 4x 90 | 128.0 MHz | 460
+
    **SE** (Solver Equivalent) - The performance of one solver slice running at 100 MHz.
 
    It appears the power supply on the VC707 board is failing us on the cramped