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Remove potential endless loop, and cleanup Core trait a bit. #88

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Nov 18, 2019
Merged

Remove potential endless loop, and cleanup Core trait a bit. #88

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91 changes: 43 additions & 48 deletions probe-rs/src/collection/cores/m0.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
use crate::memory::MI;
use crate::probe::debug_probe::{CpuInformation, DebugProbeError, MasterProbe};
use crate::target::{BasicRegisterAddresses, Core, CoreRegister, CoreRegisterAddress};
use crate::probe::debug_probe::{DebugProbeError, MasterProbe};
use crate::target::{
BasicRegisterAddresses, Core, CoreInformation, CoreRegister, CoreRegisterAddress,
};
use bitfield::bitfield;

use super::CortexDump;
Expand All @@ -16,10 +18,10 @@ bitfield! {
pub s_sleep, _: 18;
pub s_halt, _: 17;
pub s_regrdy, _: 16;
pub _, set_c_maskints: 3;
pub _, set_c_step: 2;
pub _, set_c_halt: 1;
pub _, set_c_debugen: 0;
pub c_maskings, set_c_maskints: 3;
pub c_step, set_c_step: 2;
pub c_halt, set_c_halt: 1;
pub c_debugen, set_c_debugen: 0;
}

impl Dhcsr {
Expand All @@ -30,6 +32,7 @@ impl Dhcsr {
/// Software must write 0xA05F to this field to enable write accesses to bits
/// [15:0], otherwise the processor ignores the write access.
pub fn enable_write(&mut self) {
self.0 &= !(0xffff << 16);
self.0 |= 0xa05f << 16;
}
}
Expand Down Expand Up @@ -318,7 +321,7 @@ impl Core for M0 {
self.wait_for_core_register_transfer(mi)
}

fn halt(&self, mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn halt(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
// TODO: Generic halt support

let mut value = Dhcsr(0);
Expand All @@ -328,11 +331,13 @@ impl Core for M0 {

mi.write32(Dhcsr::ADDRESS, value.into())?;

self.wait_for_core_halted(mi)?;

// try to read the program counter
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CpuInformation { pc: pc_value })
Ok(CoreInformation { pc: pc_value })
}

fn run(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
Expand All @@ -344,7 +349,7 @@ impl Core for M0 {
mi.write32(Dhcsr::ADDRESS, value.into()).map_err(Into::into)
}

fn step(&self, mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn step(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
let mut value = Dhcsr(0);
// Leave halted state.
// Step one instruction.
Expand All @@ -362,41 +367,43 @@ impl Core for M0 {
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CpuInformation { pc: pc_value })
Ok(CoreInformation { pc: pc_value })
}

fn reset(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
// Set THE AIRCR.SYSRESETREQ control bit to 1 to request a reset. (ARM V6 ARM, B1.5.16)

let reset_val = (0x05FA << 16) | (1 << 2);

const AIRCR: u32 = 0xE000_ED0C;
let mut value = Aircr(0);
value.vectkey();
value.set_sysresetreq(true);

mi.write32(AIRCR, reset_val)?;
mi.write32(Aircr::ADDRESS, value.into())?;

Ok(())
}

fn reset_and_halt(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
fn reset_and_halt(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
// Ensure debug mode is enabled
let dhcsr_val = Dhcsr(mi.read32(Dhcsr::ADDRESS)?);
if !dhcsr_val.c_debugen() {
let mut dhcsr = Dhcsr(0);
dhcsr.set_c_debugen(true);
dhcsr.enable_write();
mi.write32(Dhcsr::ADDRESS, dhcsr.into())?;
}

// Set the vc_corereset bit in the DEMCR register.
// This will halt the core after reset.
let demcr_val = Demcr(mi.read32(Demcr::ADDRESS)?);
if !demcr_val.vc_corereset() {
let mut demcr_enabled = demcr_val;
demcr_enabled.set_vc_corereset(true);
mi.write32(Demcr::ADDRESS, demcr_enabled.into())?;
}

let mut value = Aircr(0);
value.vectkey();
value.set_sysresetreq(true);

mi.write32(Aircr::ADDRESS, value.into())?;
self.reset(mi)?;

loop {
let dhcsr_val = Dhcsr(mi.read32(Dhcsr::ADDRESS)?);
if dhcsr_val.s_halt() || dhcsr_val.s_lockup() || dhcsr_val.s_sleep() {
break;
}
}
self.wait_for_core_halted(mi)?;

const XPSR_THUMB: u32 = 1 << 24;
let xpsr_value = self.read_core_reg(mi, REGISTERS.XPSR)?;
Expand All @@ -406,7 +413,11 @@ impl Core for M0 {

mi.write32(Demcr::ADDRESS, demcr_val.into())?;

Ok(())
// try to read the program counter
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CoreInformation { pc: pc_value })
}

fn get_available_breakpoint_units(&self, mi: &mut MasterProbe) -> Result<u32, DebugProbeError> {
Expand All @@ -425,7 +436,7 @@ impl Core for M0 {

mi.write32(BpCtrl::ADDRESS, value.into())?;

self.wait_for_core_halted(mi)
Ok(())
}

fn set_breakpoint(&self, mi: &mut MasterProbe, addr: u32) -> Result<(), DebugProbeError> {
Expand All @@ -437,15 +448,7 @@ impl Core for M0 {

mi.write32(BpCompx::ADDRESS, value.into())?;

self.wait_for_core_halted(mi)
}

fn enable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!();
}

fn disable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!();
Ok(())
}

fn read_block8(
Expand Down Expand Up @@ -478,7 +481,7 @@ impl Core for FakeM0 {
unimplemented!();
}

fn halt(&self, _mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn halt(&self, _mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
unimplemented!()
}

Expand All @@ -487,15 +490,15 @@ impl Core for FakeM0 {
}

/// Steps one instruction and then enters halted state again.
fn step(&self, _mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn step(&self, _mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
unimplemented!()
}

fn reset(&self, _mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
unimplemented!()
}

fn reset_and_halt(&self, _mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
fn reset_and_halt(&self, _mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
unimplemented!()
}

Expand Down Expand Up @@ -541,14 +544,6 @@ impl Core for FakeM0 {
unimplemented!()
}

fn enable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!()
}

fn disable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!()
}

fn read_block8(
&self,
_mi: &mut MasterProbe,
Expand Down
65 changes: 34 additions & 31 deletions probe-rs/src/collection/cores/m4.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
use crate::memory::MI;
use crate::probe::debug_probe::{CpuInformation, DebugProbeError, MasterProbe};
use crate::target::{BasicRegisterAddresses, Core, CoreRegister, CoreRegisterAddress};
use crate::probe::debug_probe::{DebugProbeError, MasterProbe};
use crate::target::{
BasicRegisterAddresses, Core, CoreInformation, CoreRegister, CoreRegisterAddress,
};
use bitfield::bitfield;

bitfield! {
Expand All @@ -14,10 +16,10 @@ bitfield! {
pub s_halt, _: 17;
pub s_regrdy, _: 16;
pub c_snapstall, set_c_snapstall: 5;
pub _, set_c_maskints: 3;
pub _, set_c_step: 2;
pub _, set_c_halt: 1;
pub _, set_c_debugen: 0;
pub c_maskings, set_c_maskints: 3;
pub c_step, set_c_step: 2;
pub c_halt, set_c_halt: 1;
pub c_debugen, set_c_debugen: 0;
}

impl Dhcsr {
Expand All @@ -28,6 +30,7 @@ impl Dhcsr {
/// Software must write 0xA05F to this field to enable write accesses to bits
/// [15:0], otherwise the processor ignores the write access.
pub fn enable_write(&mut self) {
self.0 &= !(0xffff << 16);
self.0 |= 0xa05f << 16;
}
}
Expand Down Expand Up @@ -269,7 +272,7 @@ impl Core for M4 {
self.wait_for_core_register_transfer(mi)
}

fn halt(&self, mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn halt(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
// TODO: Generic halt support

let mut value = Dhcsr(0);
Expand All @@ -279,11 +282,13 @@ impl Core for M4 {

mi.write32(Dhcsr::ADDRESS, value.into())?;

self.wait_for_core_halted(mi)?;

// try to read the program counter
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CpuInformation { pc: pc_value })
Ok(CoreInformation { pc: pc_value })
}

fn run(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
Expand All @@ -295,7 +300,7 @@ impl Core for M4 {
mi.write32(Dhcsr::ADDRESS, value.into()).map_err(Into::into)
}

fn step(&self, mi: &mut MasterProbe) -> Result<CpuInformation, DebugProbeError> {
fn step(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
let mut value = Dhcsr(0);
// Leave halted state.
// Step one instruction.
Expand All @@ -313,7 +318,7 @@ impl Core for M4 {
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CpuInformation { pc: pc_value })
Ok(CoreInformation { pc: pc_value })
}

fn reset(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
Expand All @@ -327,26 +332,28 @@ impl Core for M4 {
Ok(())
}

fn reset_and_halt(&self, mi: &mut MasterProbe) -> Result<(), DebugProbeError> {
fn reset_and_halt(&self, mi: &mut MasterProbe) -> Result<CoreInformation, DebugProbeError> {
// Ensure debug mode is enabled
let dhcsr_val = Dhcsr(mi.read32(Dhcsr::ADDRESS)?);
if !dhcsr_val.c_debugen() {
let mut dhcsr = Dhcsr(0);
dhcsr.set_c_debugen(true);
dhcsr.enable_write();
mi.write32(Dhcsr::ADDRESS, dhcsr.into())?;
}

// Set the vc_corereset bit in the DEMCR register.
// This will halt the core after reset.
let demcr_val = Demcr(mi.read32(Demcr::ADDRESS)?);
if !demcr_val.vc_corereset() {
let mut demcr_enabled = demcr_val;
demcr_enabled.set_vc_corereset(true);
mi.write32(Demcr::ADDRESS, demcr_enabled.into())?;
}

let mut value = Aircr(0);
value.vectkey();
value.set_sysresetreq(true);

mi.write32(Aircr::ADDRESS, value.into())?;
self.reset(mi)?;

loop {
let dhcsr_val = Dhcsr(mi.read32(Dhcsr::ADDRESS)?);
if dhcsr_val.s_halt() || dhcsr_val.s_lockup() || dhcsr_val.s_sleep() {
break;
}
}
self.wait_for_core_halted(mi)?;

const XPSR_THUMB: u32 = 1 << 24;
let xpsr_value = self.read_core_reg(mi, REGISTERS.XPSR)?;
Expand All @@ -356,7 +363,11 @@ impl Core for M4 {

mi.write32(Demcr::ADDRESS, demcr_val.into())?;

Ok(())
// try to read the program counter
let pc_value = self.read_core_reg(mi, REGISTERS.PC)?;

// get pc
Ok(CoreInformation { pc: pc_value })
}

fn get_available_breakpoint_units(
Expand All @@ -378,14 +389,6 @@ impl Core for M4 {
unimplemented!();
}

fn enable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!();
}

fn disable_breakpoint(&self, _mi: &mut MasterProbe, _addr: u32) -> Result<(), DebugProbeError> {
unimplemented!();
}

fn read_block8(
&self,
mi: &mut MasterProbe,
Expand Down
5 changes: 0 additions & 5 deletions probe-rs/src/probe/debug_probe.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -262,11 +262,6 @@ impl MasterProbe {
}
}

#[derive(Debug)]
pub struct CpuInformation {
pub pc: u32,
}

impl<REGISTER> APAccess<MemoryAP, REGISTER> for MasterProbe
where
REGISTER: APRegister<MemoryAP>,
Expand Down