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| *.runs/ | ||
| *.jou | ||
| *.log | ||
| *.str | ||
| *.data/wt |
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| VC707\_experimental | ||
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| WARNING: Currently UNTESTED! | ||
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| This project tests a fully pipelined DSP48E1 based mining core, on the VC707 development kit. It has been successfully routed at 400MHz, or 400MH/s. | ||
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| The DSP48E1 design uses DSP48E1 slices to perform almost all of the additions. DSP48E1 slices are rated up to ~500MHz at -3 speed grade. Logic slices are used to perform the non-linear math, and store pipeline registers. | ||
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| This project uses a UART communication module. The VC707, conveniently, has a USB-UART bridge on-board. | ||
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| If using the getwork protocol, new work should be sent as follows (Python pseudo-code): | ||
| uart_write (data[128:128+24] + midstate + '\n') | ||
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| For example: | ||
| 1571d1be4de695931a26942190f741afb3ab06f1a582c5c85ee7a561912b25a7cd09c060a89b3c2a73a48e22 | ||
| followed by a newline. After which, after a bit of time, the device should return `0E33337A` and two other results. It will then stop until new work is given to it. | ||
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| Golden nonces are written to UART by the Virtex when found (newline separated). The Virtex will also report its on-die temperature every 4 seconds, again over UART. To differentiate between a golden nonce and a temperature reading, just look at the length of the number returned (which is hex encoded). A nonce will be 8 characters, followed by a newline. A temperature reading will be 4 characters, followed by a newline. | ||
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| The temperature readings are interpreted like so: | ||
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| Temp (C) = reading * 503.975 / 65536 - 273.15 | ||
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| The operating range is 0C to 85C. Never exceed 125C! There are no automatic fail-safes currently enabled (yet). | ||
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| There is no mining script (yet). |
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projects/VC707_experimental/VC707_experimental.data/constrs_1/designprops.xml
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| <?xml version="1.0"?> | ||
| <Compat Version="1" Minor="4"> | ||
| <CompatParts> | ||
| </CompatParts> | ||
| <ConfigModes> | ||
| <Mode Id="JTAG"/> | ||
| </ConfigModes> | ||
| <PortProps> | ||
| </PortProps> | ||
| </Compat> | ||
|
|
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projects/VC707_experimental/VC707_experimental.data/constrs_1/fileset.xml
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <DARoots Version="1" Minor="30"> | ||
| <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> | ||
| <Filter Type="Constrs"/> | ||
| <File Path="$PDATADIR/constrs_1/designprops.xml"> | ||
| <FileInfo SFType="CompatPartsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/designprops.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| <Attr Name="UsedIn" Val="simulation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PDATADIR/constrs_1/usercols.xml"> | ||
| <FileInfo SFType="UserColsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/usercols.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| <Attr Name="UsedIn" Val="simulation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_pins.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_timing.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <Config> | ||
| <Option Name="TargetConstrsFile" Val="$PPRDIR/vc707_pins.xdc"/> | ||
| <Option Name="ConstrsType" Val="XDC"/> | ||
| </Config> | ||
| </FileSet> | ||
| </DARoots> |
4 changes: 4 additions & 0 deletions
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projects/VC707_experimental/VC707_experimental.data/constrs_1/usercols.xml
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| <?xml version="1.0"?> | ||
| <UserColInfo Version="1" Minor="0"> | ||
| </UserColInfo> | ||
|
|
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projects/VC707_experimental/VC707_experimental.data/hw/hwsession_1.xml
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| Original file line number | Diff line number | Diff line change |
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <hwsession version="1" minor="1"> | ||
| <probeset name="hwsession" active="false"/> | ||
| </hwsession> |
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projects/VC707_experimental/VC707_experimental.data/runs/impl_1.psg
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| <?xml version="1.0"?> | ||
| <Strategy Version="1" Minor="2"> | ||
| <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2013"> | ||
| <Desc>Vivado Implementation Defaults</Desc> | ||
| </StratHandle> | ||
| <Step Id="init_design"> | ||
| </Step> | ||
| <Step Id="opt_design"> | ||
| </Step> | ||
| <Step Id="power_opt_design"> | ||
| </Step> | ||
| <Step Id="place_design"> | ||
| </Step> | ||
| <Step Id="post_place_power_opt_design"> | ||
| </Step> | ||
| <Step Id="phys_opt_design"> | ||
| </Step> | ||
| <Step Id="route_design"> | ||
| </Step> | ||
| <Step Id="write_bitstream"> | ||
| </Step> | ||
| </Strategy> | ||
|
|
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projects/VC707_experimental/VC707_experimental.data/runs/impl_1/constrs_in.xml
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <DARoots Version="1" Minor="30"> | ||
| <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> | ||
| <Filter Type="Constrs"/> | ||
| <File Path="$PDATADIR/constrs_1/designprops.xml"> | ||
| <FileInfo SFType="CompatPartsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/designprops.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PDATADIR/constrs_1/usercols.xml"> | ||
| <FileInfo SFType="UserColsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/usercols.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_pins.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_timing.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <Config> | ||
| <Option Name="TargetConstrsFile" Val="$PPRDIR/vc707_pins.xdc"/> | ||
| <Option Name="ConstrsType" Val="XDC"/> | ||
| </Config> | ||
| </FileSet> | ||
| </DARoots> |
23 changes: 23 additions & 0 deletions
23
projects/VC707_experimental/VC707_experimental.data/runs/impl_1/impl_1.psg
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| <?xml version="1.0"?> | ||
| <Strategy Version="1" Minor="2"> | ||
| <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2013"> | ||
| <Desc>Vivado Implementation Defaults</Desc> | ||
| </StratHandle> | ||
| <Step Id="init_design"> | ||
| </Step> | ||
| <Step Id="opt_design"> | ||
| </Step> | ||
| <Step Id="power_opt_design"> | ||
| </Step> | ||
| <Step Id="place_design"> | ||
| </Step> | ||
| <Step Id="post_place_power_opt_design"> | ||
| </Step> | ||
| <Step Id="phys_opt_design"> | ||
| </Step> | ||
| <Step Id="route_design"> | ||
| </Step> | ||
| <Step Id="write_bitstream"> | ||
| </Step> | ||
| </Strategy> | ||
|
|
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55
projects/VC707_experimental/VC707_experimental.data/runs/runs.xml
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| <?xml version="1.0"?> | ||
| <Runs Version="1" Minor="9"> | ||
| <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1761-2" LaunchPart="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1367734230"> | ||
| <File Type="RDS-UTIL" Name="fpgaminer_top_utilization_synth.rpt"/> | ||
| <File Type="RUN-STRAT" Name="$PDATADIR/runs/synth_1/synth_1.psg"/> | ||
| <File Type="RDS-UTIL-PB" Name="fpgaminer_top_utilization_synth.pb"/> | ||
| <File Type="RDS-DCP" Name="fpgaminer_top.dcp"/> | ||
| <File Type="VDS-TIMINGSUMMARY" Name="fpgaminer_top_timing_summary_synth.rpt"/> | ||
| <File Type="VDS-TIMING-PB" Name="fpgaminer_top_timing_summary_synth.pb"/> | ||
| <File Type="PA-TCL" Name="fpgaminer_top.tcl"/> | ||
| <File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/> | ||
| <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/> | ||
| <File Type="RDS-RDS" Name="fpgaminer_top.rds"/> | ||
| </Run> | ||
| <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc7vx485tffg1761-2" LaunchPart="xc7vx485tffg1761-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1367734952"> | ||
| <File Type="RUN-STRAT" Name="$PDATADIR/runs/impl_1/impl_1.psg"/> | ||
| <File Type="OPT-DRC" Name="fpgaminer_top_drc_opted.rpt"/> | ||
| <File Type="PLACE-IO" Name="fpgaminer_top_io_placed.rpt"/> | ||
| <File Type="PLACE-CLK" Name="fpgaminer_top_clock_utilization_placed.rpt"/> | ||
| <File Type="PLACE-UTIL" Name="fpgaminer_top_utilization_placed.rpt"/> | ||
| <File Type="PLACE-UTIL-PB" Name="fpgaminer_top_utilization_placed.pb"/> | ||
| <File Type="PLACE-CTRL" Name="fpgaminer_top_control_sets_placed.rpt"/> | ||
| <File Type="PLACE-SIMILARITY" Name="fpgaminer_top_incremental_reuse_placed.rpt"/> | ||
| <File Type="ROUTE-DRC" Name="fpgaminer_top_drc_routed.rpt"/> | ||
| <File Type="PA-TCL" Name="fpgaminer_top.tcl"/> | ||
| <File Type="ROUTE-DRC-PB" Name="fpgaminer_top_drc_routed.pb"/> | ||
| <File Type="ROUTE-PWR" Name="fpgaminer_top_power_routed.rpt"/> | ||
| <File Type="ROUTE-PWR-SUM" Name="fpgaminer_top_power_summary_routed.pb"/> | ||
| <File Type="ROUTE-STATUS" Name="fpgaminer_top_route_status.rpt"/> | ||
| <File Type="ROUTE-STATUS-PB" Name="fpgaminer_top_route_status.pb"/> | ||
| <File Type="ROUTE-DCP" Name="fpgaminer_top_routed.dcp"/> | ||
| <File Type="ROUTE-TIMINGSUMMARY" Name="fpgaminer_top_timing_summary_routed.rpt"/> | ||
| <File Type="ROUTE-TIMING-PB" Name="fpgaminer_top_timing_summary_routed.pb"/> | ||
| <File Type="OPT-DCP" Name="fpgaminer_top_opt.dcp"/> | ||
| <File Type="PLACE-DCP" Name="fpgaminer_top_placed.dcp"/> | ||
| <File Type="PWROPT-DCP" Name="fpgaminer_top_pwropt.dcp"/> | ||
| <File Type="RDI-RDI" Name="fpgaminer_top.rdi"/> | ||
| <File Type="PA-DCP" Name="fpgaminer_top.dcp"/> | ||
| <File Type="POSTPLACE-PWROPT-DCP" Name="fpgaminer_top_postplace_pwropt.dcp"/> | ||
| <File Type="PWROPT-DRC" Name="fpgaminer_top_drc_pwropted.rpt"/> | ||
| <File Type="PHYSOPT-DCP" Name="fpgaminer_top_physopt.dcp"/> | ||
| <File Type="PHYSOPT-DRC" Name="fpgaminer_top_drc_physopted.rpt"/> | ||
| <File Type="BG-BIT" Name="fpgaminer_top.bit"/> | ||
| <File Type="BG-DRC" Name="fpgaminer_top.drc"/> | ||
| <File Type="BG-BGN" Name="fpgaminer_top.bgn"/> | ||
| <File Type="BG-BIN" Name="fpgaminer_top.bin"/> | ||
| <File Type="BITSTR-MSK" Name="fpgaminer_top.msk"/> | ||
| <File Type="BITSTR-RBT" Name="fpgaminer_top.rbt"/> | ||
| <File Type="BITSTR-NKY" Name="fpgaminer_top.nky"/> | ||
| <File Type="BITSTR-BMM" Name="fpgaminer_top_bd.bmm"/> | ||
| <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/> | ||
| <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/> | ||
| </Run> | ||
| </Runs> | ||
|
|
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projects/VC707_experimental/VC707_experimental.data/runs/synth_1.psg
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,9 @@ | ||
| <?xml version="1.0"?> | ||
| <Strategy Version="1" Minor="2"> | ||
| <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2013"> | ||
| <Desc>Vivado Synthesis Defaults</Desc> | ||
| </StratHandle> | ||
| <Step Id="synth_design"> | ||
| </Step> | ||
| </Strategy> | ||
|
|
38 changes: 38 additions & 0 deletions
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projects/VC707_experimental/VC707_experimental.data/runs/synth_1/constrs_in.xml
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <DARoots Version="1" Minor="30"> | ||
| <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> | ||
| <Filter Type="Constrs"/> | ||
| <File Path="$PDATADIR/constrs_1/designprops.xml"> | ||
| <FileInfo SFType="CompatPartsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/designprops.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PDATADIR/constrs_1/usercols.xml"> | ||
| <FileInfo SFType="UserColsDb"> | ||
| <Attr Name="ImportPath" Val="$PDATADIR/constrs_1/usercols.xml"/> | ||
| <Attr Name="ImportTime" Val="1365939190"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_pins.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <File Path="$PPRDIR/vc707_timing.xdc"> | ||
| <FileInfo> | ||
| <Attr Name="UsedInSynthesis" Val="1"/> | ||
| <Attr Name="UsedInImplementation" Val="1"/> | ||
| <Attr Name="UsedIn" Val="synthesis"/> | ||
| <Attr Name="UsedIn" Val="implementation"/> | ||
| </FileInfo> | ||
| </File> | ||
| <Config> | ||
| <Option Name="TargetConstrsFile" Val="$PPRDIR/vc707_pins.xdc"/> | ||
| <Option Name="ConstrsType" Val="XDC"/> | ||
| </Config> | ||
| </FileSet> | ||
| </DARoots> |
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