Added LX150_makomk_Test. Tests makomk's code on a Xilinx Spartan 6 LX…

…150T. Currently the code fits at LOOP_LOG2 and compiles correctly. 50MHz. However the chip does not return correct Golden Nonces. Need to debug in simulation.
progranism · Jul 22, 2011 · 6d6a429 · 6d6a429
1 parent f98b441
commit 6d6a429
Show file tree

Hide file tree

Showing 15 changed files with 22,876 additions and 4 deletions.
diff --git a/projects/LX150_Test/hdl/pipelined_normal_top.v b/projects/LX150_Test/hdl/pipelined_normal_top.v
@@ -10,7 +10,7 @@
 
 module pipelined_normal_top (CLK_100MHZ);
 
-	parameter LOOP_LOG2 = 2;
+	parameter LOOP_LOG2 = 1;
 
 	localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
 	localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;

diff --git a/projects/LX150_Test/xilinx_fpgaminer.xise b/projects/LX150_Test/xilinx_fpgaminer.xise
@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="../../src/sha-256-functions.v" xil_pn:type="FILE_VERILOG">
@@ -159,7 +159,7 @@
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
@@ -284,7 +284,6 @@
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>

diff --git a/projects/LX150_makomk_Test/.gitignore b/projects/LX150_makomk_Test/.gitignore
@@ -0,0 +1 @@
+iseconfig
diff --git a/projects/LX150_makomk_Test/README.md b/projects/LX150_makomk_Test/README.md
@@ -0,0 +1,4 @@
+This is a port of the normal Verilog code to run on a Xilinx device, done by teknohog (http://forum.bitcoin.org/index.php?action=profile;u=575).
+Modified by makomk.
+
+Experimenting with it on an LX150T device.
diff --git a/projects/LX150_makomk_Test/constraints/fpgaminer_top.ucf b/projects/LX150_makomk_Test/constraints/fpgaminer_top.ucf
@@ -0,0 +1,7 @@
+#NET CLK_100MHZ           LOC = U23  | IOSTANDARD = LVCMOS25;  # "CLK_100MHZ"
+#TIMESPEC TS_CLK_100MHZ = PERIOD CLK_100MHZ 10 ns HIGH 50 %;
+
+#Net CLK_100MHZ TNM_NET = sys_clk_pin;
+Net "CLK_100MHZ" TNM_NET = "CLK_100MHZ"  |  LOC=U23 | IOSTANDARD = LVCMOS25;
+#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+TIMESPEC "TS_CLK_100MHZ" = PERIOD "CLK_100MHZ" 10 ns HIGH 50%;
diff --git a/projects/LX150_makomk_Test/hdl/chipscope_icon.ngc b/projects/LX150_makomk_Test/hdl/chipscope_icon.ngc