First commit. Code ported from existing project, cleaned up, and veri…

…fied to be somewhat user friendly.

.gitignore

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+*~
+*.swp
+db
+incremental_db
+work
+quartus_output

README.md

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+Terasic DE2-115 FPGA Open-Source Bitcoin Miner
+==============================================
+
+--------------------------------------------------------------------------------
+Copyright (C) 2011 fpgaminer@bitcoin-mining.com
+See LICENSE.txt
+
+
+Purpose
+-------
+
+To promote the free and open development of an FPGA based Bitcoin mining solution.
+http://www.weusecoins.com/
+http://bitcoin.org/
+
+
+Project Status
+--------------
+
+Project is fully functional and allows mining of Bitcoins both in a Pool and Solo.
+Can also support Namecoin mining with a minor modification (tested but not documented).
+
+**Current Performance:** 80 MHash/s
+*Note: The included default configuration file, and source files, are built for
+50 MHash/s performance (downclocked). This is meant to prevent damage to your valuable
+chip if you don't provide an appropriate cooling solution.*
+
+
+Installation Instructions
+-------------------------
+
+
+### Required Equipment:
+* DE2-115 Development Kit
+* USB Cable
+* Windows PC (Linux is also supported, but not documented)
+* Altera's Quartus II (installed on PC)
+
+
+###Instructions:
+
+####Do These Once:
+
+1) *IMPORTANT*: Please remove the clear acrylic cover on your DE2-115 board. This will restrict
+air flow and may cause the chip to overheat.
+
+2) Navigate to 'scripts/mine' and EDIT 'mine.tcl' (open in Notepad or other text editor)
+
+3) Locate the following lines:
+
+    set url "http://btcguild.com:8332"
+    set userpass "youremailhere@example.com:yourpasswordhere"
+
+
+Edit accordingly (N.B. the script has only been tested with btcguild and deepbit so far).
+
+4) Save and close 'mine.tcl'
+
+####Do these each time you want to run the miner:
+
+1) Connect the DE2-115 Development Kit to your PC through USB, connect its power, and turn it on.
+
+2) Ensure that the DE2-115's drivers have been installed successfully on your PC.
+Consult the DE2-115 User Guide for more information on setting up the DE2-115.
+
+3) Navigate to 'scripts/program' and run 'program-fpga-board.bat'.
+
+4) Follow the instructions provided by the program-fpga-board script.
+Select the correct cable and programming file.
+Once programming has succeeded, the DE2-115 is now ready to mine!
+
+*Note: This script sometimes fails immediately upon execution. Please try running it again.*
+
+5) Run 'mine.bat'
+
+6) If working correctly, 'mine.bat' will leave a console window open which will fill with diagnostic information as it runs.
+
+7) Profit!
+
+
+####Notes:
+* You need to re-program the DE2-115 every time it is powered off and on again. Repeat steps 1 through 7 for subsequent uses.
+* Your PC needs to stay on and connected to the internet. It is acting like a controller for the FPGA,
+feeding it data and getting back valid hashes.
+
+
+Thank You!
+--------------------
+
+--------------------
+
+
+
+> -----BEGIN PGP SIGNED MESSAGE-----
+> Hash: SHA1
+> 
+> fpgaminer@bitcoin-mining.com
+> 
+> Donations are most welcome! 1E1XgiJAzm1Wn7ZWuhkryzBoViBJ7CcRCQ
+> -----BEGIN PGP SIGNATURE-----
+> Version: GnuPG v1.4.11 (MingW32)
+> 
+> iQIcBAEBAgAGBQJN1ckDAAoJEFFoGj2A5YKRTmQP/2S/97/LlsNIflOhV+DNF28U
+> YlSQeAqFtQqlpJmwIcPp71sPa/WSpop0v00ciec+mQJoJVGaofWvkdP462gTGyES
+> NTWbSDeAGR2ARp8DUHNhHFSef83JOS+YqXygvtDCNJjlyZXd7PDFhg4GWN4jhLhZ
+> CWwTKVP8Q4QUg1tNLpqLyCKJYtmqgB45XXfXE8coepdfRjeETwqy8b4ODYHWNCQE
+> X9Ej9sPFcBtPWB1B+h+NQq5aKPvL1LLahwJ/MB7GYiIkuFhMtcrKiXTMT8j9b3IK
+> AGcrCTcMtbjMuADtf9GGkmtmO6/omaEfgojhOFm1l2k+nYPIYVO4HobAIuIJCImm
+> KqlhYXqIayBf8DESzbfSWpD1f0lpS16cLval/Hnx5Hk7CP3FCdyTe9RGrn4BcAi1
+> CDPIwoOHd0C2o4zqMmsj14MvfjtoUw+NI7BhY5WoVHm04zHN9nyIZmjAPFrp+qM4
+> BBaFFJ6tn4mbpUWPG8Iqm3iJqMFPcwNZu9S7GUbKqjlz2rn4FcwNypZqndvdJFus
+> G1YkLbI7e0rL3MTf89FCl+XvRfn5cUVAaRDjZVQJOnk/Xsm6D2kiibuwGN+O5Pqj
+> IxYZOoxGimwKKzQf0Arr5B+dtNfiSVdupu5etluuiLSboAODECZt83f0L5t+FBhm
+> 2vYNW7VNeLA2ZnfDhCHU
+> =VdDC
+> -----END PGP SIGNATURE-----
+
+

fpgaminer.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 19:43:05  May 18, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.0"
+DATE = "19:43:05  May 18, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "fpgaminer"
+

fpgaminer.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors.  Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 05:05:52  March 02, 2011
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY fpgaminer_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:52:09  MAY 05, 2011"
+set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_Y2 -to osc_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to osc_clk
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name VERILOG_FILE src/sha256_transform.v
+set_global_assignment -name VERILOG_FILE src/fpgaminer_top.v
+set_global_assignment -name VERILOG_FILE src/main_pll.v
+set_global_assignment -name VERILOG_FILE src/virtual_wire.v
+set_global_assignment -name VERILOG_FILE "src/sha-256-functions.v"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus_output
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS OFF -section_id eda_simulation
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING OFF -section_id eda_simulation
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME moogerfoogin -section_id eda_simulation
+set_global_assignment -name POWER_USE_PVA OFF
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 65%
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpgaminer.sdc

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+##
+#
+# Copyright (c) 2011 fpgaminer@bitcoin-mining.com
+#
+#
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+##
+
+create_clock -period 20.000 -name osc_clk osc_clk
+
+derive_pll_clocks
+derive_clock_uncertainty
+

scripts/mine/mine.bat

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+%QUARTUS_ROOTDIR%\bin\quartus_stp -t mine.tcl
+PAUSE