temporarily disable translation; update emode encoding

Change-Id: If22d22c50f509d319a8a132d3cedc8ceca2ff91b
project-starch · Sep 25, 2023 · 516f2ab · 516f2ab
1 parent 93e7865
commit 516f2ab
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Showing 4 changed files with 5 additions and 4 deletions.
diff --git a/src/arch/riscvcapstone/mmu.hh b/src/arch/riscvcapstone/mmu.hh
@@ -91,7 +91,8 @@ class MMU : public BaseMMU
 
     void translateTiming(const RequestPtr& req, ThreadContext* tc,
             Translation* translation, Mode mode) override {
-        if(tc->cwrld() == 1) {
+        //if(tc->cwrld() == 1) {
+        if(1) {
             DPRINTF(CapstoneMem, "translate %llx\n", req->getVaddr());
             req->setPaddr(req->getVaddr()); // simply pass through
             translation->finish(NoFault, req, tc, mode);

diff --git a/src/arch/riscvcapstone/o3/cpu.cc b/src/arch/riscvcapstone/o3/cpu.cc
@@ -572,7 +572,7 @@ CPU::startup()
         ctrv.getRegVal().rawCapVal() = (uint128_t)*cap;
         isa[tid]->setTaggedMiscReg(1, ctrv); //capmiscreg_cinit
 
-        cwrld[tid] = 1;
+        cwrld[tid] = 0;
     }
 }
 

diff --git a/src/arch/riscvcapstone/pmp.cc b/src/arch/riscvcapstone/pmp.cc
@@ -249,7 +249,7 @@ PMP::shouldCheckPMP(RiscvcapstoneISA::PrivilegeMode pmode,
 
     bool secure_world = tc->cwrld();
 
-    return ((cond1 || cond2 || cond3) && !secure_world);
+    return ((cond1 || cond2 || cond3) && /*!secure_world*/ 0);
 }
 
 AddrRange

diff --git a/src/arch/riscvcapstone/regs/misc.hh b/src/arch/riscvcapstone/regs/misc.hh
@@ -385,7 +385,7 @@ enum CSRIndex
     //Capstone CSRs
     CSR_TVAL = 0x801, //exception data
     CSR_CAUSE = 0x802, //exception cause
-    CSR_EMODE = 0x804 //encoding mode
+    CSR_EMODE = 0x803 //encoding mode
 };
 
 //Capability CSRs