Skip to content

Commit

Permalink
fix format bugs
Browse files Browse the repository at this point in the history
  • Loading branch information
Mingkai-Li committed Aug 31, 2023
1 parent c797641 commit 301fd5a
Showing 1 changed file with 62 additions and 48 deletions.
110 changes: 62 additions & 48 deletions docs/spike-debug.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -56,117 +56,131 @@ S:: Secure world

== Debugging Instructions

[r]
=== Revocation Tree

****
RCUPDATE
.*RCUPDATE*
[%collapsible]
====
****
Update the revocation tree node with node id `x[rs1]` by `x[rs2]`.
====
****
====

****
ALLOC
.*ALLOC*
[%collapsible]
====
****
Allocate a new revocation tree node whose parent node has a node id `x[rs1]`, and write the node id of the new node to `x[rd]`.
====
****
====

****
REV
.*REV*
[%collapsible]
====
****
Revoke the revocation tree node (and the nodes of its subtree) with node id `x[rs1]`.
====
****
====

=== Capability Manipulation

****
CAPCREATE
.*CAPCREATE*
[%collapsible]
====
****
Make the tag of the register `x[rd]` to refer to a capability.
====
****
====

****
CAPTYPE
.*CAPTYPE*
[%collapsible]
====
****
Set `x[rd].type` to `x[rs1]`.
====
****
====

****
CAPNODE
.*CAPNODE*
[%collapsible]
====
****
Set `x[rd].node` to `x[rs1]`.
====
****
====

****
CAPPERM
.*CAPPERM*
[%collapsible]
====
****
Set `x[rd].perm` to `x[rs1]`.
====
****
====

****
CAPBOUND
.*CAPBOUND*
[%collapsible]
====
****
. Set `x[rd].base` to `x[rs1]`.
. If `x[rs2]` is not `zero`, set `x[rd].end` to `x[rs2]`.
====
****
====

****
CAPASYNC
.*CAPASYNC*
[%collapsible]
====
****
Set `x[rd].async` to `x[rs1]`.
====
****
====

****
CAPREG
.*CAPREG*
[%collapsible]
====
****
Set `x[rd].reg` to `x[rs1]`.
====
****
====

=== Memory

****
CAPPRINT
====
Print the content in `x[rs1]` to the console.
.*TAGSET*
[%collapsible]
====
****

****
TAGSET
====
Set the tag of the CLEN-bit aligned memory region containing the memory address `x[rs1]` to refer to a capability if `x[rs2]` is not `zero`, or to refer to an integer register otherwise.
====
****
====

****
TAGGET
.*TAGGET*
[%collapsible]
====
****
If the tag of the CLEN-bit aligned memory region containing the memory address `x[rs1]` refers to a capability, set `x[rd]` to `1`; otherwise, set `x[rd]` to `0`.
====
****
====

=== Others

.*CAPPRINT*
[%collapsible]
====
****
Print the content in `x[rs1]` to the console.
****
SETWORLD
====
Set `cwrld` to `0` if `x[rs1]` is `zero`, or to `1` otherwise.

.*SETWORLD*
[%collapsible]
====
****

Set `cwrld` to `0` if `x[rs1]` is `zero`, or to `1` otherwise.
****
SETEH
====
Set `ceh` to `x[rs1]`.

.*SETEH*
[%collapsible]
====
****
Set `ceh` to `x[rs1]`.
****
====

0 comments on commit 301fd5a

Please sign in to comment.