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acrn-config: add xml to support TGL RVP board
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1. Use acrn-configure tool to generate xml files to support TGL
RVP board. You need make menuconfig as guide in github, and then
comiple as following:
  make hypervisor BOARD_FILE=path/xxx.xml SCENARIO_FILE=path/yyy.xml

2. Also uos launch script can be generated by acrn-configure tool with the
uos luanch xml file

Tracked-On: #4181
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
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@mgcao @wenlingz
mgcao authored and wenlingz committed Dec 9, 2019
1 parent 1fe1afd commit 65a5532
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283 changes: 283 additions & 0 deletions misc/acrn-config/xmls/board-xmls/tgl-rvp.xml
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<acrn-config board="tgl-rvp">
<BIOS_INFO>
BIOS Information
Vendor: Intel Corporation
Version: TGLSFWI1.R00.2321.A08.1909162051
Release Date: 09/16/2019
</BIOS_INFO>

<BASE_BOARD_INFO>
Base Board Information
Manufacturer: Intel Corporation
Product Name: TigerLake U DDR4 SODIMM RVP
Version: 1
</BASE_BOARD_INFO>

<PCI_DEVICE>
00:00.0 Host bridge: Intel Corporation Device 9a14
00:02.0 VGA compatible controller: Intel Corporation Device 9a49
Region 0: Memory at ab000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at 80000000 (64-bit, prefetchable) [size=256M]
Region 0: Memory at 00000000ad000000 (64-bit, non-prefetchable)
Region 2: Memory at 0000000000000000 (64-bit, prefetchable)
00:04.0 Signal processing controller: Intel Corporation Device 9a03
Region 0: Memory at ac280000 (64-bit, non-prefetchable) [disabled] [size=128K]
00:07.0 PCI bridge: Intel Corporation Device 9a23
00:07.1 PCI bridge: Intel Corporation Device 9a25
00:07.2 PCI bridge: Intel Corporation Device 9a27
00:07.3 PCI bridge: Intel Corporation Device 9a29
00:08.0 System peripheral: Intel Corporation Device 9a11
Region 0: Memory at ac300000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:0a.0 Signal processing controller: Intel Corporation Device 9a0d (rev 01)
Region 0: Memory at ac2f0000 (64-bit, non-prefetchable) [size=32K]
00:0d.0 USB controller: Intel Corporation Device 9a13
Region 0: Memory at ac2c0000 (64-bit, non-prefetchable) [size=64K]
00:0d.2 System peripheral: Intel Corporation Device 9a1b
Region 0: Memory at ac200000 (64-bit, non-prefetchable) [size=256K]
Region 2: Memory at ac301000 (64-bit, non-prefetchable) [size=4K]
00:0d.3 System peripheral: Intel Corporation Device 9a1d
Region 0: Memory at ac240000 (64-bit, non-prefetchable) [size=256K]
Region 2: Memory at ac302000 (64-bit, non-prefetchable) [size=4K]
00:12.0 Serial controller: Intel Corporation Device a0fc
Region 0: Memory at ac2d0000 (64-bit, non-prefetchable) [size=64K]
00:14.0 USB controller: Intel Corporation Device a0ed
Region 0: Memory at ac2e0000 (64-bit, non-prefetchable) [size=64K]
00:14.2 RAM memory: Intel Corporation Device a0ef
Region 0: Memory at ac2f8000 (64-bit, non-prefetchable) [disabled] [size=16K]
Region 2: Memory at ac303000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:15.0 Serial bus controller [0c80]: Intel Corporation Device a0e8
Region 0: Memory at 3f400000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:15.1 Serial bus controller [0c80]: Intel Corporation Device a0e9
Region 0: Memory at 3f401000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:15.2 Serial bus controller [0c80]: Intel Corporation Device a0ea
Region 0: Memory at 3f402000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:15.3 Serial bus controller [0c80]: Intel Corporation Device a0eb
Region 0: Memory at 3f403000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:16.0 Communication controller: Intel Corporation Device a0e0
Region 0: Memory at ac308000 (64-bit, non-prefetchable) [size=4K]
00:19.0 Serial bus controller [0c80]: Intel Corporation Device a0c5
Region 0: Memory at 3f404000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:19.1 Serial bus controller [0c80]: Intel Corporation Device a0c6
Region 0: Memory at 3f405000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:1d.0 PCI bridge: Intel Corporation Device a0b0
00:1e.0 Communication controller: Intel Corporation Device a0a8
Region 0: Memory at 3f406000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:1e.3 Serial bus controller [0c80]: Intel Corporation Device a0ab
Region 0: Memory at 3f407000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:1f.0 ISA bridge: Intel Corporation Device a082
00:1f.3 Multimedia audio controller: Intel Corporation Device a0c8
Region 0: Memory at ac2fc000 (64-bit, non-prefetchable) [disabled] [size=16K]
Region 4: Memory at ac000000 (64-bit, non-prefetchable) [disabled] [size=1M]
00:1f.4 SMBus: Intel Corporation Device a0a3
Region 0: Memory at ac30d000 (64-bit, non-prefetchable) [disabled] [size=256]
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device a0a4
Region 0: Memory at 3f408000 (32-bit, non-prefetchable) [size=4K]
00:1f.6 Ethernet controller: Intel Corporation Device 15fc
Region 0: Memory at ac2a0000 (32-bit, non-prefetchable) [disabled] [size=128K]
ad:00.0 Non-Volatile memory controller: Intel Corporation Device f1a8 (rev 03)
Region 0: Memory at ac100000 (64-bit, non-prefetchable) [size=16K]
</PCI_DEVICE>

<PCI_VID_PID>
00:00.0 0600: 8086:9a14
00:02.0 0300: 8086:9a49
00:04.0 1180: 8086:9a03
00:07.0 0604: 8086:9a23
00:07.1 0604: 8086:9a25
00:07.2 0604: 8086:9a27
00:07.3 0604: 8086:9a29
00:08.0 0880: 8086:9a11
00:0a.0 1180: 8086:9a0d (rev 01)
00:0d.0 0c03: 8086:9a13
00:0d.2 0880: 8086:9a1b
00:0d.3 0880: 8086:9a1d
00:12.0 0700: 8086:a0fc
00:14.0 0c03: 8086:a0ed
00:14.2 0500: 8086:a0ef
00:15.0 0c80: 8086:a0e8
00:15.1 0c80: 8086:a0e9
00:15.2 0c80: 8086:a0ea
00:15.3 0c80: 8086:a0eb
00:16.0 0780: 8086:a0e0
00:19.0 0c80: 8086:a0c5
00:19.1 0c80: 8086:a0c6
00:1d.0 0604: 8086:a0b0
00:1e.0 0780: 8086:a0a8
00:1e.3 0c80: 8086:a0ab
00:1f.0 0601: 8086:a082
00:1f.3 0401: 8086:a0c8
00:1f.4 0c05: 8086:a0a3
00:1f.5 0c80: 8086:a0a4
00:1f.6 0200: 8086:15fc
ad:00.0 0108: 8086:f1a8 (rev 03)
</PCI_VID_PID>

<WAKE_VECTOR_INFO>
#define WAKE_VECTOR_32 0x3498700CUL
#define WAKE_VECTOR_64 0x34987018UL
</WAKE_VECTOR_INFO>

<RESET_REGISTER_INFO>
#define RESET_REGISTER_ADDRESS 0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE 0x6U
</RESET_REGISTER_INFO>

<PM_INFO>
#define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO
#define PM1A_EVT_BIT_WIDTH 0x20U
#define PM1A_EVT_BIT_OFFSET 0x0U
#define PM1A_EVT_ADDRESS 0x1800UL
#define PM1A_EVT_ACCESS_SIZE 0x2U
#define PM1B_EVT_SPACE_ID SPACE_SYSTEM_IO
#define PM1B_EVT_BIT_WIDTH 0x0U
#define PM1B_EVT_BIT_OFFSET 0x0U
#define PM1B_EVT_ADDRESS 0x0UL
#define PM1B_EVT_ACCESS_SIZE 0x2U
#define PM1A_CNT_SPACE_ID SPACE_SYSTEM_IO
#define PM1A_CNT_BIT_WIDTH 0x10U
#define PM1A_CNT_BIT_OFFSET 0x0U
#define PM1A_CNT_ADDRESS 0x1804UL
#define PM1A_CNT_ACCESS_SIZE 0x2U
#define PM1B_CNT_SPACE_ID SPACE_SYSTEM_IO
#define PM1B_CNT_BIT_WIDTH 0x0U
#define PM1B_CNT_BIT_OFFSET 0x0U
#define PM1B_CNT_ADDRESS 0x0UL
#define PM1B_CNT_ACCESS_SIZE 0x2U
</PM_INFO>

<S3_INFO>
#define S3_PKG_VAL_PM1A 0x5U
#define S3_PKG_VAL_PM1B 0U
#define S3_PKG_RESERVED 0x0U
</S3_INFO>

<S5_INFO>
#define S5_PKG_VAL_PM1A 0x7U
#define S5_PKG_VAL_PM1B 0U
#define S5_PKG_RESERVED 0x0U
</S5_INFO>

<DRHD_INFO>
#define DRHD_COUNT 6U

#define DRHD0_DEV_CNT 0x1U
#define DRHD0_SEGMENT 0x0U
#define DRHD0_FLAGS 0x0U
#define DRHD0_REG_BASE 0xFED90000UL
#define DRHD0_IGNORE true
#define DRHD0_DEVSCOPE0_TYPE 0x1U
#define DRHD0_DEVSCOPE0_ID 0x0U
#define DRHD0_DEVSCOPE0_BUS 0x0U
#define DRHD0_DEVSCOPE0_PATH 0x10U

#define DRHD1_DEV_CNT 0x1U
#define DRHD1_SEGMENT 0x0U
#define DRHD1_FLAGS 0x0U
#define DRHD1_REG_BASE 0xFED84000UL
#define DRHD1_IGNORE false
#define DRHD1_DEVSCOPE0_TYPE 0x2U
#define DRHD1_DEVSCOPE0_ID 0x0U
#define DRHD1_DEVSCOPE0_BUS 0x0U
#define DRHD1_DEVSCOPE0_PATH 0x38U

#define DRHD2_DEV_CNT 0x1U
#define DRHD2_SEGMENT 0x0U
#define DRHD2_FLAGS 0x0U
#define DRHD2_REG_BASE 0xFED85000UL
#define DRHD2_IGNORE false
#define DRHD2_DEVSCOPE0_TYPE 0x2U
#define DRHD2_DEVSCOPE0_ID 0x0U
#define DRHD2_DEVSCOPE0_BUS 0x0U
#define DRHD2_DEVSCOPE0_PATH 0x39U

#define DRHD3_DEV_CNT 0x1U
#define DRHD3_SEGMENT 0x0U
#define DRHD3_FLAGS 0x0U
#define DRHD3_REG_BASE 0xFED86000UL
#define DRHD3_IGNORE false
#define DRHD3_DEVSCOPE0_TYPE 0x2U
#define DRHD3_DEVSCOPE0_ID 0x0U
#define DRHD3_DEVSCOPE0_BUS 0x0U
#define DRHD3_DEVSCOPE0_PATH 0x3aU

#define DRHD4_DEV_CNT 0x1U
#define DRHD4_SEGMENT 0x0U
#define DRHD4_FLAGS 0x0U
#define DRHD4_REG_BASE 0xFED87000UL
#define DRHD4_IGNORE false
#define DRHD4_DEVSCOPE0_TYPE 0x2U
#define DRHD4_DEVSCOPE0_ID 0x0U
#define DRHD4_DEVSCOPE0_BUS 0x0U
#define DRHD4_DEVSCOPE0_PATH 0x3bU

#define DRHD5_DEV_CNT 0x0U
#define DRHD5_SEGMENT 0x0U
#define DRHD5_FLAGS 0x1U
#define DRHD5_REG_BASE 0xFED91000UL
#define DRHD5_IGNORE false

</DRHD_INFO>

<CPU_BRAND>
"Genuine Intel(R) CPU 0000 @ 1.00GHz"
</CPU_BRAND>

<CX_INFO>
{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x61U, 0x00U}, /* C2 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
</CX_INFO>

<PX_INFO>
{0x4B1UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002400UL, 0x002400UL}, /* P0 */
{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL}, /* P1 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P2 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P3 */
{0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P4 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P5 */
{0x2BCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000700UL, 0x000700UL}, /* P6 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P7 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P8 */
{0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P9 */
</PX_INFO>

<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xc0000000UL
</MMCFG_BASE_INFO>

<CLOS_INFO>
clos supported by cache:L2
clos max:8
</CLOS_INFO>

<SYSTEM_RAM_INFO>
00001000-0009efff : System RAM
00100000-1fdfffff : System RAM
20000000-30d48fff : System RAM
34c4f000-34c4ffff : System RAM
100000000-4c0bfffff : System RAM
</SYSTEM_RAM_INFO>

<BLOCK_DEVICE_INFO>
/dev/nvme0n1p3: TYPE="ext4"
</BLOCK_DEVICE_INFO>

<TTYS_INFO>
seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
</TTYS_INFO>

<AVAILABLE_IRQ_INFO>
3, 5, 6, 7, 10, 11, 12, 13, 14, 15
</AVAILABLE_IRQ_INFO>

<TOTAL_MEM_INFO>
16155896 kB
</TOTAL_MEM_INFO>

<CPU_PROCESSOR_INFO>
0, 1, 2, 3
</CPU_PROCESSOR_INFO>

</acrn-config>
98 changes: 98 additions & 0 deletions misc/acrn-config/xmls/config-xmls/tgl-rvp/industry.xml
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<?xml version='1.0' encoding='utf-8'?>
<acrn-config board="tgl-rvp" scenario="industry">
<vm id="0">
<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">SOS_VM</load_order>
<name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
<uuid configurable="0" desc="vm uuid">dbbbd434-7a57-4216-a12c-2201f1ab0240</uuid>
<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
<guest_flag />
</guest_flags>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<memory>
<start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
<size configurable="0" desc="The memory size in Bytes for the VM">0x20000000</size>
</memory>
<os_config>
<name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
<kern_type desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">KERNEL_BZIMAGE</kern_type>
<kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
<bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
</os_config>
<vuart id="0">
<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address." readonly="true">SOS_COM1_BASE</base>
<irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
</vuart>
<vuart id="1">
<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">2</target_vm_id>
<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
</vuart>
<pci_dev_num configurable="0" desc="pci devices number">SOS_EMULATED_PCI_DEV_NUM</pci_dev_num>
<pci_devs configurable="0" desc="pci devices list">sos_pci_devs</pci_devs>
<board_private>
<rootfs desc="rootfs for Linux kernel">/dev/nvme0n1p3</rootfs>
<console desc="ttyS console for Linux kernel">/dev/ttyS0</console>
<bootargs desc="Specify kernel boot arguments"> rw rootwait console=ttyS0 consoleblank=0 no_timer_check quiet loglevel=3
i915.nuclear_pageflip=1 i915.avail_planes_per_pipe=0x01010F i915.domain_plane_owners=0x011111110000 i915.enable_gvt=1
</bootargs>
</board_private>
</vm>
<vm id="1">
<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
<uuid configurable="0" desc="vm uuid">d2795438-25d6-11e8-864e-cb7a18b34643</uuid>
<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
<guest_flag />
</guest_flags>
<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
<pcpu_id>1</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
</epc_section>
<vuart id="0">
<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
</vuart>
<vuart id="1">
<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
</vuart>
</vm>
<vm id="2">
<load_order desc="Specify the VM by its load order: PRE_LAUNCHED_VM, SOS_VM or POST_LAUNCHED_VM." readonly="true">POST_LAUNCHED_VM</load_order>
<uuid configurable="0" desc="vm uuid">495ae2e5-2603-4d64-af76-d4bc5a8ec0e5</uuid>
<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
<guest_flag>GUEST_FLAG_HIGHEST_SEVERITY</guest_flag>
</guest_flags>
<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
<pcpu_id>2</pcpu_id>
<pcpu_id>3</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
</epc_section>
<vuart id="0">
<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
<irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
</vuart>
<vuart id="1">
<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
<irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
</vuart>
</vm>
</acrn-config>
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