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VT-d code reshuffle #1855
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binbinwu1
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Nov 20, 2018
dmar_uint -> dmar_unit remove i in line 756 added by accident. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
binbinwu1
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Nov 20, 2018
Becuase the number of character of a line is 120. Merge lines for a statement if needed. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
binbinwu1
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Nov 20, 2018
Move move public API to the bottom part of the file. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
binbinwu1
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Nov 20, 2018
Add an internal API to do action according to action function provided, which can simplify the code. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
binbinwu1
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Nov 20, 2018
Check vtd translation enabling status when enable/disable translation inside dmar_enable/disable_translation with spinlock. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
Current code doesn't init interrupt config when resume from S3. The related register contect will be lost during S3. This patch re-init these regiters. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
In current code, DMA remapping is enabled at very early stage, when there is no device added. Devices are added to VT-d context table when creating VMs. There is potential risk that there may be device DMA transactions when DMA remapping is enabled, but the device is not added to the VT-d context table. (Eg. this could happen in UEFI enviroment when USB keyboard use in efi intenal shell.) This patch defers DMA remapping enabling until vm creation. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
1. use error code defined in errno.h instead of 1. 2. panic if error occured while adding devices to VM0 domain. 3. panic if failed to reqeust irq for iommu. The two panic added would only occurs before any VM starts running. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
Add an internal API to do action according to action function provided, which can simplify the code. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
binbinwu1
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Nov 20, 2018
Check vtd translation enabling status when enable/disable translation inside dmar_enable/disable_translation with spinlock. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
Current code doesn't init interrupt config when resume from S3. The related register contect will be lost during S3. This patch re-init these regiters. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
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Nov 20, 2018
In current code, DMA remapping is enabled at very early stage, when there is no device added. Devices are added to VT-d context table when creating VMs. There is potential risk that there may be device DMA transactions when DMA remapping is enabled, but the device is not added to the VT-d context table. (Eg. this could happen in UEFI enviroment when USB keyboard use in efi intenal shell.) This patch defers DMA remapping enabling until vm creation. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
binbinwu1
added a commit
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Nov 20, 2018
1. use error code defined in errno.h instead of 1. 2. panic if error occured while adding devices to VM0 domain. 3. panic if failed to reqeust irq for iommu. The two panic added would only occurs before any VM starts running. Tracked-On: projectacrn#1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
lijinxia
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Nov 20, 2018
dmar_uint -> dmar_unit remove i in line 756 added by accident. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
lijinxia
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Nov 20, 2018
Becuase the number of character of a line is 120. Merge lines for a statement if needed. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
lijinxia
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Nov 20, 2018
Move move public API to the bottom part of the file. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
lijinxia
pushed a commit
that referenced
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Nov 20, 2018
Add an internal API to do action according to action function provided, which can simplify the code. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
lijinxia
pushed a commit
that referenced
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Nov 20, 2018
Check vtd translation enabling status when enable/disable translation inside dmar_enable/disable_translation with spinlock. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
lijinxia
pushed a commit
that referenced
this issue
Nov 20, 2018
Current code doesn't init interrupt config when resume from S3. The related register contect will be lost during S3. This patch re-init these regiters. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
lijinxia
pushed a commit
that referenced
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Nov 20, 2018
In current code, DMA remapping is enabled at very early stage, when there is no device added. Devices are added to VT-d context table when creating VMs. There is potential risk that there may be device DMA transactions when DMA remapping is enabled, but the device is not added to the VT-d context table. (Eg. this could happen in UEFI enviroment when USB keyboard use in efi intenal shell.) This patch defers DMA remapping enabling until vm creation. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
lijinxia
pushed a commit
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Nov 20, 2018
1. use error code defined in errno.h instead of 1. 2. panic if error occured while adding devices to VM0 domain. 3. panic if failed to reqeust irq for iommu. The two panic added would only occurs before any VM starts running. Tracked-On: #1855 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
[External_System_ID] ACRN-2453 |
sainath14
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Dec 24, 2018
This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: projectacrn#1855 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
sainath14
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Dec 24, 2018
This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: projectacrn#1855 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
sainath14
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Dec 24, 2018
This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: projectacrn#1855 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
wenlingz
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Dec 24, 2018
This patch does the following changes According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers are flushed implicitly upon Remapping Hardware Caches Invalidation even on platforms that set RWBF to 1 in capability register. So removed write buffer flushing as current ACRN issues cache invalidation commands in all cases. Tracked-On: #1855 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
No regression |
mwang106
added
area: device model
type: feature
New feature
status: closed
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Jan 11, 2019
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Code cleanup and bug fix for VT-d code.
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