Increase data bus delay for the dynamic pipeline

proteus-core · Feb 3, 2023 · 6d8b80d · 6d8b80d
1 parent 968276b
commit 6d8b80d
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/riscv/Core.scala b/src/main/scala/riscv/Core.scala
@@ -297,7 +297,7 @@ object CoreDynamicSim {
 
 object CoreDynamicExtMem {
   def main(args: Array[String]) {
-    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 32))
+    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 64))
   }
 }