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A RISC Processor based on AVR instruction set

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Ultrabotix Pvt. Ltd https://www.ultrabotix.com

Processor: VEGA https://youtu.be/ObhPlSDs8TA

A Verilog Implementation of 8 bit RISC Processor based on AVR ISA

  • Core verification

Features :

a) 32 instructions including Arithmetic, Logical, Load, Store, Branch, Jump, Call, each of 16 bits frame

b) 8 bit ALU

c) 32 eight bit general purpose registers

d) 256 byte data memory

e) 512 byte program memory

f) Pipelined/Non-pipelined

g) Max operating frequency tested : 100Mhz

h) One input and one output port

i) testbench in system verilog and uvm

j) testbench in python (in progress)

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A RISC Processor based on AVR instruction set

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  • Verilog 53.5%
  • SystemVerilog 46.5%