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🐛 Fix re-naming when issued operand is flushed
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@zarubaf
zarubaf committed Sep 24, 2018
1 parent 712de20 commit b58b63d
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Showing 7 changed files with 82 additions and 69 deletions.
3 changes: 0 additions & 3 deletions README.md
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Expand Up @@ -72,8 +72,6 @@ $ riscv64-unknown-elf-gcc hello.c -o hello.elf
```
$ make verilate
$ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
```

If you want to use QuestaSim to run it you can use the following command:
Expand Down Expand Up @@ -122,7 +120,6 @@ In order to run randomized Torture tests, you first have to generate the randomi
$ ./ci/get-torture.sh
$ make torture-gen
$ make torture-rtest-verilator
```
This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.

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26 changes: 14 additions & 12 deletions bootrom/bootrom.sv
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Expand Up @@ -20,15 +20,15 @@ module bootrom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 141;
localparam int RomSize = 143;

const logic [RomSize-1:0][63:0] mem = {
64'h0064,
64'h65646e65_7478652d,
64'h73747075_72726574,
64'h6e690073_65676e61,
64'h7200656c_646e6168,
64'h70007265_6c6c6f72,
64'h00646564_6e657478,
64'h652d7374_70757272,
64'h65746e69_00736567,
64'h6e617200_656c646e,
64'h6168702c_78756e69,
64'h6c007265_6c6c6f72,
64'h746e6f63_2d747075,
64'h72726574_6e690073,
64'h6c6c6563_2d747075,
Expand Down Expand Up @@ -60,15 +60,15 @@ module bootrom (
64'h4b000000_10000000,
64'h03000000_07000000,
64'h01000000_03000000,
64'h01000000_ae000000,
64'h01000000_b4000000,
64'h10000000_03000000,
64'h00000000_30746e69,
64'h6c632c76_63736972,
64'h1b000000_0d000000,
64'h03000000_00000030,
64'h30303030_30324074,
64'h6e696c63_01000000,
64'ha7000000_00000000,
64'had000000_00000000,
64'h03000000_00007375,
64'h622d656c_706d6973,
64'h00636f73_2d657261,
Expand All @@ -91,6 +91,8 @@ module bootrom (
64'h6f6d656d_01000000,
64'h02000000_02000000,
64'h02000000_01000000,
64'ha5000000_04000000,
64'h03000000_01000000,
64'h9f000000_04000000,
64'h03000000_00006374,
64'h6e692d75_70632c76,
Expand Down Expand Up @@ -143,11 +145,11 @@ module bootrom (
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'he8020000_c2000000,
64'hf8020000_c8000000,
64'h00000000_10000000,
64'h11000000_28000000,
64'h20030000_38000000,
64'he2030000_edfe0dd0,
64'h30030000_38000000,
64'hf8030000_edfe0dd0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
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6 changes: 3 additions & 3 deletions src/clint/axi_lite_interface.sv
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Expand Up @@ -141,7 +141,7 @@ module axi_lite_interface #(
// Registers
// ------------------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
if (~rst_ni) begin
CS <= IDLE;
address_q <= '0;
trans_id_q <= '0;
Expand All @@ -159,10 +159,10 @@ module axi_lite_interface #(
`ifndef SYNTHESIS
`ifndef VERILATOR
// check that burst length is just one
assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0) && (slave.ar_size == $clog2(AXI_ADDR_WIDTH/8))))
assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
// do the same for the write channel
assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0) && (slave.aw_size == $clog2(AXI_ADDR_WIDTH/8))))
assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
`endif
`endif
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7 changes: 4 additions & 3 deletions src/clint/clint.sv
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Expand Up @@ -132,10 +132,11 @@ module clint #(
always_comb begin : irq_gen
// check that the mtime cmp register is set to a meaningful value
for (int unsigned i = 0; i < NR_CORES; i++) begin
if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i])
if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i]) begin
timer_irq_o[i] = 1'b1;
else
end else begin
timer_irq_o[i] = 1'b0;
end
end
end

Expand All @@ -155,7 +156,7 @@ module clint #(

// Registers
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
if (~rst_ni) begin
mtime_q <= 64'b0;
mtimecmp_q <= 'b0;
msip_q <= '0;
Expand Down
77 changes: 43 additions & 34 deletions src/issue_stage.sv
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Expand Up @@ -19,7 +19,7 @@ module issue_stage #(
parameter int unsigned NR_ENTRIES = 8,
parameter int unsigned NR_WB_PORTS = 4,
parameter int unsigned NR_COMMIT_PORTS = 2
)(
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

Expand Down Expand Up @@ -98,45 +98,54 @@ module issue_stage #(
// 1. Re-name
// ---------------------------------------------------------
re_name i_re_name (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( flush_i ),
.issue_instr_i ( decoded_instr_i ),
.issue_instr_valid_i ( decoded_instr_valid_i ),
.issue_ack_o ( decoded_instr_ack_o ),
.issue_instr_o ( issue_instr_rename_sb ),
.issue_instr_valid_o ( issue_instr_valid_rename_sb ),
.issue_ack_i ( issue_ack_sb_rename )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_i ( flush_i ),
.flush_unissied_instr_i ( flush_unissued_instr_i ),
.issue_instr_i ( decoded_instr_i ),
.issue_instr_valid_i ( decoded_instr_valid_i ),
.issue_ack_o ( decoded_instr_ack_o ),
.issue_instr_o ( issue_instr_rename_sb ),
.issue_instr_valid_o ( issue_instr_valid_rename_sb ),
.issue_ack_i ( issue_ack_sb_rename )
);

// ---------------------------------------------------------
// 2. Manage instructions in a scoreboard
// ---------------------------------------------------------
scoreboard #(
.NR_ENTRIES ( NR_ENTRIES ),
.NR_WB_PORTS ( NR_WB_PORTS )
scoreboard #(
.NR_ENTRIES (NR_ENTRIES ),
.NR_WB_PORTS(NR_WB_PORTS)
) i_scoreboard (
.unresolved_branch_i ( 1'b0 ),
.rd_clobber_o ( rd_clobber_sb_iro ),
.rs1_i ( rs1_iro_sb ),
.rs1_o ( rs1_sb_iro ),
.rs1_valid_o ( rs1_valid_sb_iro ),
.rs2_i ( rs2_iro_sb ),
.rs2_o ( rs2_sb_iro ),
.rs2_valid_o ( rs2_valid_iro_sb ),

.decoded_instr_i ( issue_instr_rename_sb ),
.decoded_instr_valid_i ( issue_instr_valid_rename_sb ),
.decoded_instr_ack_o ( issue_ack_sb_rename ),
.issue_instr_o ( issue_instr_sb_iro ),
.issue_instr_valid_o ( issue_instr_valid_sb_iro ),
.issue_ack_i ( issue_ack_iro_sb ),

.resolved_branch_i ( resolved_branch_i ),
.trans_id_i ( trans_id_i ),
.wbdata_i ( wbdata_i ),
.ex_i ( ex_ex_i ),
.*
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_unissued_instr_i ( flush_unissued_instr_i ),
.flush_i ( flush_i ),
.unresolved_branch_i ( 1'b0 ),

.rd_clobber_o ( rd_clobber_sb_iro ),
.rs1_i ( rs1_iro_sb ),
.rs1_o ( rs1_sb_iro ),
.rs1_valid_o ( rs1_valid_sb_iro ),
.rs2_i ( rs2_iro_sb ),
.rs2_o ( rs2_sb_iro ),
.rs2_valid_o ( rs2_valid_iro_sb ),

.commit_instr_o ( commit_instr_o ),
.commit_ack_i ( commit_ack_i ),

.decoded_instr_i ( issue_instr_rename_sb ),
.decoded_instr_valid_i ( issue_instr_valid_rename_sb ),
.decoded_instr_ack_o ( issue_ack_sb_rename ),

.issue_instr_o ( issue_instr_sb_iro ),
.issue_instr_valid_o ( issue_instr_valid_sb_iro ),
.issue_ack_i ( issue_ack_iro_sb ),
.resolved_branch_i ( resolved_branch_i ),
.trans_id_i ( trans_id_i ),
.wbdata_i ( wbdata_i ),
.ex_i ( ex_ex_i ),
.wb_valid_i ( wb_valid_i )
);

// ---------------------------------------------------------
Expand Down
3 changes: 2 additions & 1 deletion src/re_name.sv
View file
Expand Up @@ -24,6 +24,7 @@ module re_name (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i, // Flush renaming state
input logic flush_unissied_instr_i,
// from/to scoreboard
input scoreboard_entry_t issue_instr_i,
input logic issue_instr_valid_i,
Expand Down Expand Up @@ -52,7 +53,7 @@ module re_name (
re_name_table_gpr_n = re_name_table_gpr_q;
issue_instr_o = issue_instr_i;

if (issue_ack_i) begin
if (issue_ack_i && !flush_unissied_instr_i) begin
// if we acknowledge the instruction tic the corresponding destination register
re_name_table_gpr_n[issue_instr_i.rd] = re_name_table_gpr_q[issue_instr_i.rd] ^ 1'b1;
end
Expand Down
29 changes: 16 additions & 13 deletions tb/ariane_testharness.sv
View file
Expand Up @@ -14,17 +14,17 @@
// Instantiates an AXI-Bus and memories

module ariane_testharness #(
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
parameter int unsigned AXI_ID_WIDTH = 10,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned NUM_WORDS = 2**24 // memory size
)(
input logic clk_i,
input logic rst_ni,
output logic [31:0] exit_o
);
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
parameter int unsigned AXI_ID_WIDTH = 10,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned NUM_WORDS = 2**24 // memory size
)(
input logic clk_i,
input logic rst_ni,
output logic [31:0] exit_o
);

// disable test-enable
logic test_en;
Expand Down Expand Up @@ -64,6 +64,9 @@ module ariane_testharness #(
logic dmi_resp_ready;
logic dmi_resp_valid;

logic rtc_i;
assign rtc_i = 1'b0;

assign test_en = 1'b0;
assign ndmreset_n = ~ndmreset ;

Expand Down Expand Up @@ -153,7 +156,7 @@ module ariane_testharness #(
.debug_req_valid ( dmi_req_valid ),
.debug_req_ready ( debug_req_ready ),
.debug_req_bits_addr ( dmi_req.addr ),
.debug_req_bits_op ( debug_req_bits_op ),
.debug_req_bits_op ( debug_req_bits_op ),
.debug_req_bits_data ( dmi_req.data ),
.debug_resp_valid ( dmi_resp_valid ),
.debug_resp_ready ( dmi_resp_ready ),
Expand Down Expand Up @@ -298,7 +301,7 @@ module ariane_testharness #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slave ( master[1] ),
.rtc_i ( 1'b0 ),
.rtc_i ( rtc_i ),
.timer_irq_o ( timer_irq ),
.ipi_o ( ipi )
);
Expand Down

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