We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
According to the RISC-V CLIC spec, the memory layout of the memory mapped registers should be as follows:
0x1000+4*i 1B/input R or RW clicintip[i] 0x1001+4*i 1B/input RW clicintie[i] 0x1002+4*i 1B/input RW clicintattr[i] 0x1003+4*i 1B/input RW clicintctl[i] ... 0x4FFC 1B/input R or RW clicintip[4095] 0x4FFD 1B/input RW clicintie[4095] 0x4FFE 1B/input RW clicintattr[4095] 0x4FFF 1B/input RW clicintctl[4095]
The clicint[ip/ie/attr/clt] registers have a width of 1 byte. See https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-memory-map
clicint[ip/ie/attr/clt]
However, in the current implementation they are 4 bytes wide.
The text was updated successfully, but these errors were encountered:
Fixed in #7 , closing the issue
Sorry, something went wrong.
Successfully merging a pull request may close this issue.
According to the RISC-V CLIC spec, the memory layout of the memory mapped registers should be as follows:
The
clicint[ip/ie/attr/clt]registers have a width of 1 byte. See https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-memory-mapHowever, in the current implementation they are 4 bytes wide.
The text was updated successfully, but these errors were encountered: