/
rtl8195a_sdio_device.c
3177 lines (2856 loc) · 98.4 KB
/
rtl8195a_sdio_device.c
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_sdio.h"
#include "mailbox.h"
#if CONFIG_INIC_EN
#include "freertos_pmu.h"
extern struct sk_buff *rltk_wlan_alloc_skb(unsigned int total_len);
extern unsigned char *skb_put(struct sk_buff * skb, unsigned int len);
extern void inic_sdio_free_data(unsigned char *data);
#if (CONFIG_INIC_SKB_TX == 0) //pre-allocated memory for SDIO TX BD
ALIGNMTO(4) char inic_TX_Buf[SDIO_TX_BD_NUM][SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT];
#endif
#endif
extern PHAL_SDIO_ADAPTER pgSDIODev;
#ifdef CONFIG_SOC_PS_MODULE
//extern RAM_START_FUNCTION gRamWakeupFun;
extern u8 __ram_start_table_start__[];
extern _LONG_CALL_ VOID HalCpuClkConfig(u8 CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalReInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
extern VOID InfraStart(VOID);
extern VOID SleepPG(u8 Option, u32 SDuration);
extern VOID PSHalInitPlatformLogUart(VOID);
extern VOID HalReInitPlatformTimer(VOID);
extern VOID DeepStandby(u8 Option, u32 SDuration, u8 GpioOption);
extern VOID QueryRegPwrState(u8 FuncIdx, u8* RegState, u8* HwState);
#endif
/******************************************************************************
* Function Prototype Declaration
******************************************************************************/
BOOL SDIO_Device_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Device_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_IRQ_Handler(
IN VOID *pData
);
VOID SDIO_Interrupt_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Interrupt_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Enable_Interrupt(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
);
VOID SDIO_Disable_Interrupt(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
);
VOID SDIO_Clear_ISR(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
);
VOID SDIO_TxTask(
IN VOID *pData
);
VOID SDIO_RxTask(
IN VOID *pData
);
static __inline VOID SDIO_Wakeup_Task(
IN PHAL_SDIO_ADAPTER pSDIODev
);
static VOID SDIO_SetEvent(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 Event
);
static VOID SDIO_ClearEvent(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 Event
);
static BOOL SDIO_IsEventPending(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 Event
);
VOID SDIO_IRQ_Handler_BH(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_RX_IRQ_Handler_BH(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_TX_BD_Buf_Refill(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_TX_FIFO_DataReady(
IN PHAL_SDIO_ADAPTER pSDIODev
);
PSDIO_RX_PACKET SDIO_Alloc_Rx_Pkt(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Free_Rx_Pkt(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN PSDIO_RX_PACKET pPkt
);
VOID SDIO_Recycle_Rx_BD (
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Process_H2C_IOMsg(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Send_C2H_IOMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
VOID SDIO_Process_H2C_PktMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *H2CMsg
);
u8 SDIO_Send_C2H_PktMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
u8 SDIO_Process_RPWM(
IN PHAL_SDIO_ADAPTER pSDIODev
);
u8 SDIO_Process_RPWM2(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Reset_Cmd(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Return_Rx_Data(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_Register_Tx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
s8 SDIO_Rx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
s8 SDIO_Handle_MsgBlk(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN MSG_BLK *pMblk
);
#if SDIO_MP_MODE
VOID SDIO_PeriodicalTimerCallback(
void *pContex
);
u8 SDIO_MapMPCmd(
IN char *CmdStr,
IN u16 *Offset
);
VOID SDIO_DumpMPStatus(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_StatisticDump(
IN PHAL_SDIO_ADAPTER pSDIODev
);
s8 SDIO_MP_Loopback(
IN VOID *pAdapter,
IN u8 *pData,
IN u16 Offset,
IN u16 PktSize
);
s8 SDIO_MP_ContinueTx(
IN VOID *pAdapter,
IN u8 *pData,
IN u16 Offset,
IN u16 PktSize
);
VOID SDIO_MP_ContinueRx(
IN PHAL_SDIO_ADAPTER pSDIODev
);
VOID SDIO_DeviceMPApp(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u16 argc,
IN u8 *argv[]
);
#endif /* endof '#if SDIO_MP_MODE' */
/******************************************************************************
* Global Variable Declaration
******************************************************************************/
#if SDIO_MP_MODE
const SDIO_MP_CMD SDIO_MPCmdTable[] = {
{"mp_start", SDIO_MP_START},
{"mp_stop", SDIO_MP_STOP},
{"mp_loopback", SDIO_MP_LOOPBACK},
{"status", SDIO_MP_STATUS},
{"read_reg8", SDIO_MP_READ_REG8},
{"read_reg16", SDIO_MP_READ_REG16},
{"read_reg32", SDIO_MP_READ_REG32},
{"write_reg8", SDIO_MP_WRITE_REG8},
{"write_reg16", SDIO_MP_WRITE_REG16},
{"write_reg32", SDIO_MP_WRITE_REG32},
{"wakeup", SDIO_MP_WAKEUP},
{"dump", SDIO_MP_DUMP},
{"ctx", SDIO_MP_CTX},
{"crx", SDIO_MP_CRX},
{"crx_da", SDIO_MP_CRX_DA},
{"crx_stop", SDIO_MP_CRX_STOP},
{"dbg_msg", SDIO_MP_DBG_MSG}
};
const u8 MP_WlanHdr[]={
0x88,0x01,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff,
0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,
0x00,0x01,0x10,0x00,0x06,0x00};
#endif
/******************************************************************************
* External Function & Variable Declaration
******************************************************************************/
extern PHAL_SDIO_ADAPTER pgSDIODev;
extern u32 Strtoul(
IN const u8 *nptr,
IN u8 **endptr,
IN u32 base
);
/******************************************************************************
* Function: SDIO_Device_Init
* Desc: SDIO device driver initialization.
* 1. Allocate SDIO TX FIFO buffer and initial TX related register.
* 2. Allocate SDIO RX Buffer Descriptor and RX Buffer. Initial RX related
* register.
* 3. Register the Interrupt function.
* 4. Create the SDIO Task and allocate resource(Semaphore).
*
******************************************************************************/
BOOL SDIO_Device_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
)
{
int i;
SDIO_TX_PACKET *pTxPkt;
SDIO_RX_PACKET *pPkt;
SDIO_TX_BD_HANDLE *pTxBdHdl;
SDIO_RX_BD_HANDLE *pRxBdHdl;
int ret;
u32 reg_value;
DBG_SDIO_INFO("SDIO_Device_Init==>\n");
// Clean boot from wakeup bit
reg_value = HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN);
reg_value &= ~(BIT(29));
HAL_WRITE32(PERI_ON_BASE, REG_SOC_FUNC_EN, reg_value);
/* SDIO Function Enable */
SDIOD_ON_FCTRL(ON);
SDIOD_OFF_FCTRL(ON);
/* Enable Clock for SDIO function */
ACTCK_SDIOD_CCTRL(ON);
SLPCK_SDIOD_CCTRL(ON);
// Reset SDIO DMA
HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
/* Initial SDIO TX BD */
DBG_SDIO_INFO("Tx BD Init==>\n");
// TODO: initial TX BD
pSDIODev->pTXBDAddr = RtlZmalloc((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3);
if (NULL == pSDIODev->pTXBDAddr) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX_BD Err!\n");
goto SDIO_INIT_ERR;
}
pSDIODev->pTXBDAddrAligned = (PSDIO_TX_BD)(((((u32)pSDIODev->pTXBDAddr - 1) >> 2) + 1) << 2); // Make it 4-bytes aligned
HAL_SDIO_WRITE32(REG_SPDIO_TXBD_ADDR, pSDIODev->pTXBDAddrAligned);
HAL_SDIO_WRITE16(REG_SPDIO_TXBD_SIZE, SDIO_TX_BD_NUM);
/* Set TX_BUFF_UNIT_SIZE */
#if 0
reg = HAL_SDIO_READ32(REG_SPDIO_RXBD_CNT);
reg &= ~((0xff)<<8);
reg |= (SDIO_TX_BD_BUF_USIZE<<8);
HAL_SDIO_WRITE32(REG_SPDIO_RXBD_CNT, reg);
#endif
HAL_SDIO_WRITE8(REG_SPDIO_TX_BUF_UNIT_SZ, SDIO_TX_BD_BUF_USIZE);
DBG_SDIO_INFO("Tx BD Buf Unit Size(%d), Reg=0x%x\n", SDIO_TX_BD_BUF_USIZE, HAL_SDIO_READ8(REG_SPDIO_TX_BUF_UNIT_SZ));
/* Set DISPATCH_TXAGG_PKT */
HAL_SDIO_WRITE32(REG_SPDIO_AHB_DMA_CTRL, HAL_SDIO_READ32(REG_SPDIO_AHB_DMA_CTRL)|BIT31);
// Reset HW TX BD pointer
pSDIODev->TXBDWPtr = HAL_SDIO_READ32(REG_SPDIO_TXBD_WPTR);
pSDIODev->TXBDRPtr = pSDIODev->TXBDWPtr;
pSDIODev->TXBDRPtrReg = pSDIODev->TXBDWPtr;
HAL_SDIO_WRITE32(REG_SPDIO_TXBD_RPTR, pSDIODev->TXBDRPtrReg);
DBG_SDIO_INFO("TXBDWPtr=0x%x TXBDRPtr=0x%x\n", pSDIODev->TXBDWPtr, pSDIODev->TXBDRPtr);
pSDIODev->pTXBDHdl = (PSDIO_TX_BD_HANDLE)RtlZmalloc(SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE));
if (NULL == pSDIODev->pTXBDHdl) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX_BD Handle Err!\n");
goto SDIO_INIT_ERR;
}
for (i=0;i<SDIO_TX_BD_NUM;i++)
{
pTxBdHdl = pSDIODev->pTXBDHdl + i;
pTxBdHdl->pTXBD = pSDIODev->pTXBDAddrAligned + i;
#if CONFIG_INIC_EN
#if CONFIG_INIC_SKB_TX
//allocate wlan skb here
pTxBdHdl->skb = rltk_wlan_alloc_skb(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT);
DBG_SDIO_INFO("SDIO_Device_Init: pTxBdHdl->pkt @ 0x%x\n", pTxBdHdl->skb);
if(pTxBdHdl->skb)
pTxBdHdl->pTXBD->Address = (u32)pTxBdHdl->skb->tail;
else
DBG_SDIO_ERR("SDIO_Device_Init: rltk_wlan_alloc_skb (%d) failed!\n", SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT);
#else
pTxBdHdl->pTXBD->Address = (u32)(&inic_TX_Buf[i][0]);
#endif
#else
// Allocate buffer for each TX BD
pTxBdHdl->pTXBD->Address = (u32)RtlMalloc(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT);
#if SDIO_DEBUG
pSDIODev->MemAllocCnt++;
#endif
#endif
if (NULL == (u32*)(pTxBdHdl->pTXBD->Address)) {
// Memory Allocate Failed
int j;
for (j=0;j<i;j++) {
pTxBdHdl = pSDIODev->pTXBDHdl + j;
pTxBdHdl->pTXBD = pSDIODev->pTXBDAddrAligned + j;
if (pTxBdHdl->pTXBD->Address) {
#if CONFIG_INIC_EN
#if CONFIG_INIC_SKB_TX
//free wlan skb here
dev_kfree_skb_any(pTxBdHdl->skb);
#endif
pTxBdHdl->pTXBD->Address =(u32)NULL;
#else
RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT));
#endif
}
}
goto SDIO_INIT_ERR;
}
pTxBdHdl->isFree = 1;
DBG_SDIO_INFO("TX_BD%d @ 0x%x 0x%x\n", i, pTxBdHdl, pTxBdHdl->pTXBD);
}
#if (CONFIG_INIC_EN == 0)
RtlInitListhead(&pSDIODev->FreeTxPktList); // Init the list for free packet handler
/* Allocate memory for TX Packets handler */
pSDIODev->pTxPktHandler = (SDIO_TX_PACKET *)(RtlZmalloc(sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM));
if (NULL == pSDIODev->pTxPktHandler) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX PKT Handler Err!\n");
goto SDIO_INIT_ERR;
}
/* Add all TX packet handler into the Free Queue(list) */
for (i=0;i<SDIO_TX_PKT_NUM;i++)
{
pTxPkt = pSDIODev->pTxPktHandler + i;
RtlListInsertTail(&pTxPkt->list, &pSDIODev->FreeTxPktList);
}
#endif
/* Init RX BD and RX Buffer */
pSDIODev->pRXBDAddr = RtlZmalloc((SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7);
if (NULL == pSDIODev->pRXBDAddr) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX_BD Err!\n");
goto SDIO_INIT_ERR;
}
pSDIODev->pRXBDAddrAligned = (PSDIO_RX_BD)(((((u32)pSDIODev->pRXBDAddr - 1) >> 3) + 1) << 3); // Make it 8-bytes aligned
HAL_SDIO_WRITE32(REG_SPDIO_RXBD_ADDR, pSDIODev->pRXBDAddrAligned);
HAL_SDIO_WRITE16(REG_SPDIO_RXBD_SIZE, SDIO_RX_BD_NUM);
// Set the threshold of free RX BD count to trigger interrupt
HAL_SDIO_WRITE16(REG_SPDIO_RX_BD_FREE_CNT, RX_BD_FREE_TH);
DBG_SDIO_INFO("Rx BD Free Cnt(%d), Reg=0x%x\n", RX_BD_FREE_TH, HAL_SDIO_READ16(REG_SPDIO_RX_BD_FREE_CNT));
pSDIODev->pRXBDHdl = (PSDIO_RX_BD_HANDLE)RtlZmalloc(SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE));
if (NULL == pSDIODev->pRXBDHdl) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX_BD Handle Err!\n");
goto SDIO_INIT_ERR;
}
for (i=0;i<SDIO_RX_BD_NUM;i++)
{
pRxBdHdl = pSDIODev->pRXBDHdl + i;
pRxBdHdl->pRXBD = pSDIODev->pRXBDAddrAligned + i;
pRxBdHdl->isFree = 1;
DBG_SDIO_INFO("RX_BD%d @ 0x%x 0x%x\n", i, pRxBdHdl, pRxBdHdl->pRXBD);
}
RtlInitListhead(&pSDIODev->FreeRxPktList); // Init the list for free packet handler
/* Allocate memory for RX Packets handler */
pSDIODev->pRxPktHandler = (SDIO_RX_PACKET *)(RtlZmalloc(sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM));
if (NULL == pSDIODev->pRxPktHandler) {
DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX PKT Handler Err!\n");
goto SDIO_INIT_ERR;
}
/* Add all RX packet handler into the Free Queue(list) */
for (i=0;i<SDIO_RX_PKT_NUM;i++)
{
pPkt = pSDIODev->pRxPktHandler + i;
RtlListInsertTail(&pPkt->list, &pSDIODev->FreeRxPktList);
}
RtlInitListhead(&pSDIODev->RxPktList); // Init the list for RX packet to be send to the SDIO bus
// RtlInitListhead(&pSDIODev->RecyclePktList); // Init the list for packet to be recycled after the SDIO RX DMA is done
RtlMutexInit(&pSDIODev->RxMutex);
#if SDIO_DEBUG
RtlMutexInit(&pSDIODev->StatisticMutex);
#endif
/* Create a Semaphone for SDIO Sync control */
#if !TASK_SCHEDULER_DISABLED
RtlInitSema(&(pSDIODev->TxSema), 0);
if (NULL == pSDIODev->TxSema){
DBG_SDIO_ERR("SDIO_Device_Init Create Semaphore Err!\n");
goto SDIO_INIT_ERR;
}
RtlInitSema(&(pSDIODev->RxSema), 0);
if (NULL == pSDIODev->RxSema){
DBG_SDIO_ERR("SDIO_Device_Init Create RX Semaphore Err!\n");
goto SDIO_INIT_ERR;
}
/* create a Mailbox for other driver module to send message to SDIO driver */
pSDIODev->pMBox = RtlMailboxCreate(MBOX_ID_SDIO, SDIO_MAILBOX_SIZE, &(pSDIODev->RxSema));
if (NULL == pSDIODev->pMBox) {
DBG_SDIO_ERR("SDIO_Device_Init Create Mailbox Err!\n");
goto SDIO_INIT_ERR;
}
#if SDIO_MP_MODE
pSDIODev->pPeriodTimer = RtlTimerCreate("SDIO_Periodical", SDIO_PERIODICAL_TIMER_INTERVAL, SDIO_PeriodicalTimerCallback, pSDIODev, 1);
#endif
/* Create the SDIO task */
#ifdef PLATFORM_FREERTOS
ret = xTaskCreate( SDIO_TxTask, "SDIO_TX_TASK", ((1024*2)/sizeof(portBASE_TYPE)), (void *)pSDIODev, SDIO_TASK_PRIORITY + PRIORITIE_OFFSET, &pSDIODev->xSDIOTxTaskHandle);
if (pdTRUE != ret )
{
DBG_SDIO_ERR("SDIO_Device_Init: Create Task Err(%d)!\n", ret);
goto SDIO_INIT_ERR;
}
ret = xTaskCreate( SDIO_RxTask, "SDIO_RX_TASK", ((1024*1)/sizeof(portBASE_TYPE)), (void *)pSDIODev, SDIO_TASK_PRIORITY + PRIORITIE_OFFSET, &pSDIODev->xSDIORxTaskHandle);
if (pdTRUE != ret )
{
DBG_SDIO_ERR("SDIO_Device_Init: Create RX Task Err(%d)!\n", ret);
goto SDIO_INIT_ERR;
}
#endif
#endif // end of "#if !TASK_SCHEDULER_DISABLED"
#if SDIO_MP_MODE
//1 for MP mode test only
pSDIODev->MP_ModeEn = 1;
// SDIO_Register_Tx_Callback(pSDIODev, (VOID *)SDIO_MP_Loopback, (VOID *) pSDIODev);
// pSDIODev->MP_LoopBackEn = 1;
//End
#endif
#if TASK_SCHEDULER_DISABLED
/* enable the interrupt */
SDIO_Interrupt_Init(pSDIODev);
/* Indicate the Host system that the TX/RX is ready */
HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \
HAL_SDIO_READ8(REG_SPDIO_CPU_IND)|BIT_SYSTEM_TRX_RDY_IND);
#endif
pSDIODev->CRPWM = HAL_SDIO_READ8(REG_SPDIO_CRPWM);
pSDIODev->CRPWM2 = HAL_SDIO_READ16(REG_SPDIO_CRPWM2);
// Indicate Host this is a iNIC FW
pSDIODev->CCPWM2 |= CPWM2_INIC_FW_RDY_BIT;
pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT;
HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2);
#if !PURE_SDIO_INIC
#ifdef CONFIG_SOC_PS_MODULE
{
REG_POWER_STATE SDIOPwrState;
// To register a new peripheral device power state
SDIOPwrState.FuncIdx = SDIOD;
SDIOPwrState.PwrState = ACT;
RegPowerState(SDIOPwrState);
}
#endif
#endif
DBG_SDIO_INFO("<==SDIO_Device_Init\n");
return SUCCESS;
SDIO_INIT_ERR:
#if !TASK_SCHEDULER_DISABLED
if (pSDIODev->TxSema) {
RtlFreeSema(&pSDIODev->TxSema);
pSDIODev->TxSema = NULL;
}
if (pSDIODev->RxSema) {
RtlFreeSema(&pSDIODev->RxSema);
pSDIODev->RxSema = NULL;
}
#endif
if (pSDIODev->RxMutex) {
RtlMutexFree(&pSDIODev->RxMutex);
}
#if SDIO_DEBUG
if (pSDIODev->StatisticMutex) {
RtlMutexFree(&pSDIODev->StatisticMutex);
}
#endif
if (pSDIODev->pRxPktHandler) {
RtlMfree((u8*)pSDIODev->pRxPktHandler, sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM);
pSDIODev->pRxPktHandler = NULL;
}
if (pSDIODev->pRXBDHdl) {
RtlMfree((u8 *)pSDIODev->pRXBDHdl, SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE));
pSDIODev->pRXBDHdl = NULL;
}
if (pSDIODev->pRXBDAddr) {
RtlMfree((u8 *)pSDIODev->pRXBDAddr, (SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7);
pSDIODev->pRXBDAddr = NULL;
}
#if (CONFIG_INIC_EN == 0)
if (pSDIODev->pTxPktHandler) {
RtlMfree((u8 *)pSDIODev->pTxPktHandler, (sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM));
pSDIODev->pTxPktHandler = NULL;
}
#endif
if ((pSDIODev->pTXBDHdl) && (pSDIODev->pTXBDAddr)) {
for (i=0;i<SDIO_TX_BD_NUM;i++)
{
pTxBdHdl = pSDIODev->pTXBDHdl + i;
if (pTxBdHdl->pTXBD->Address) {
#if CONFIG_INIC_EN
#if CONFIG_INIC_SKB_TX
//free wlan skb here
dev_kfree_skb_any(pTxBdHdl->skb);
#endif
#else
RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT));
#endif
pTxBdHdl->pTXBD->Address = (u32)NULL;
}
}
}
if (pSDIODev->pTXBDHdl) {
RtlMfree((u8 *)pSDIODev->pTXBDHdl, (SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE)));
pSDIODev->pTXBDHdl = NULL;
}
if (pSDIODev->pTXBDAddr) {
RtlMfree(pSDIODev->pTXBDAddr, ((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3));
pSDIODev->pTXBDAddr = NULL;
pSDIODev->pTXBDAddrAligned = NULL;
}
#if !TASK_SCHEDULER_DISABLED
if (pSDIODev->pMBox) {
RtlMailboxDel(pSDIODev->pMBox);
pSDIODev->pMBox = NULL;
}
#if SDIO_MP_MODE
if (pSDIODev->pPeriodTimer) {
RtlTimerDelete(pSDIODev->pPeriodTimer);
pSDIODev->pPeriodTimer = NULL;
}
#endif
#endif
return FAIL;
}
/******************************************************************************
* Function: SDIO_Device_DeInit
* Desc: SDIO device driver free resource. This function should be called in
* a task.
* 1. Free TX FIFO buffer
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
//TODO: Call this function in a task
VOID SDIO_Device_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
)
{
int i=0;
SDIO_TX_BD_HANDLE *pTxBdHdl;
if (NULL == pSDIODev)
return;
// Indicate the Host that Ameba is InActived
pSDIODev->CCPWM2 = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
pSDIODev->CCPWM2 &= ~(CPWM2_ACT_BIT);
pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT;
HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2);
#if !TASK_SCHEDULER_DISABLED
/* Exit the SDIO task */
#if 0
// if this function is called by TX Task, then the TX task cannot be stopped
while (1) {
SDIO_SetEvent(pSDIODev, SDIO_EVENT_EXIT);
SDIO_Wakeup_Task(pSDIODev);
if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_TX_STOPPED) &&
SDIO_IsEventPending(pSDIODev, (u32)SDIO_EVENT_RX_STOPPED)) {
SDIO_ClearEvent(pSDIODev, SDIO_EVENT_EXIT);
break; // break the while loop
}
RtlMsleepOS(10);
i++;
if (i> 100) {
DBG_SDIO_ERR("SDIO_Device_DeInit: Delete SDIO Task Failed with Timeout\n");
break;
}
}
#endif
#if SDIO_MP_MODE
if (pSDIODev->pPeriodTimer) {
RtlTimerDelete(pSDIODev->pPeriodTimer);
pSDIODev->pPeriodTimer = NULL;
}
#endif
/* Delete the Mailbox */
if (pSDIODev->pMBox) {
RtlMailboxDel(pSDIODev->pMBox);
pSDIODev->pMBox = NULL;
}
/* Delete the Semaphore */
if (pSDIODev->TxSema) {
RtlFreeSema(&pSDIODev->TxSema);
pSDIODev->TxSema = NULL;
}
if (pSDIODev->RxSema) {
RtlFreeSema(&pSDIODev->RxSema);
pSDIODev->RxSema = NULL;
}
#endif
if (pSDIODev->RxMutex) {
RtlMutexFree(&pSDIODev->RxMutex);
}
#if SDIO_DEBUG
if (pSDIODev->StatisticMutex) {
RtlMutexFree(&pSDIODev->StatisticMutex);
}
#endif
if (pSDIODev->pRxPktHandler) {
RtlMfree((u8*)pSDIODev->pRxPktHandler, sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM);
pSDIODev->pRxPktHandler = NULL;
}
if (pSDIODev->pRXBDHdl) {
RtlMfree((u8 *)pSDIODev->pRXBDHdl, SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE));
pSDIODev->pRXBDHdl = NULL;
}
/* Free RX BD */
if (pSDIODev->pRXBDAddr) {
RtlMfree((u8 *)pSDIODev->pRXBDAddr, (SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7);
pSDIODev->pRXBDAddr = NULL;
}
/* Free TX FIFO Buffer */
for (i=0;i<SDIO_TX_BD_NUM;i++)
{
pTxBdHdl = pSDIODev->pTXBDHdl + i;
if (pTxBdHdl->pTXBD->Address) {
#if CONFIG_INIC_EN
#if CONFIG_INIC_SKB_TX
//free wlan skb here
dev_kfree_skb_any(pTxBdHdl->skb);
#endif
#else
RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT));
#endif
pTxBdHdl->pTXBD->Address = (u32)NULL;
}
}
#if (CONFIG_INIC_EN == 0)
if (pSDIODev->pTxPktHandler) {
RtlMfree((u8 *)pSDIODev->pTxPktHandler, (sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM));
pSDIODev->pTxPktHandler = NULL;
}
#endif
if (pSDIODev->pTXBDHdl) {
RtlMfree((u8 *)pSDIODev->pTXBDHdl, (SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE)));
pSDIODev->pTXBDHdl = NULL;
}
if (pSDIODev->pTXBDAddr) {
RtlMfree(pSDIODev->pTXBDAddr, ((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3));
pSDIODev->pTXBDAddr = NULL;
pSDIODev->pTXBDAddrAligned = NULL;
}
SDIO_Disable_Interrupt(pSDIODev, 0xffff);
SDIO_Interrupt_DeInit(pSDIODev);
// Reset SDIO DMA
HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
/* Enable Clock for SDIO function */
// ACTCK_SDIOD_CCTRL(OFF);
/* SDIO Function Enable */
// SDIOD_ON_FCTRL(OFF);
SDIOD_OFF_FCTRL(OFF);
}
#if TASK_SCHEDULER_DISABLED
/******************************************************************************
* Function: SDIO_TaskUp
* Desc: For the Task scheduler no running case, use this function to run the
* SDIO task main loop.
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
VOID SDIO_TaskUp(
IN PHAL_SDIO_ADAPTER pSDIODev
)
{
u16 ISRStatus;
// DiagPrintf("SDIO_TaskUp==>\n");
pSDIODev->EventSema++;
if (pSDIODev->EventSema > 1000) {
pSDIODev->EventSema = 1000;
}
if (pSDIODev->EventSema == 1) {
while (pSDIODev->EventSema > 0) {
ISRStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS);
pSDIODev->IntStatus |= ISRStatus;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, ISRStatus); // clean the ISR
SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ|SDIO_EVENT_C2H_DMA_DONE);
SDIO_TxTask(pSDIODev);
SDIO_RxTask(pSDIODev);
pSDIODev->EventSema--;
}
}
// DiagPrintf("<==SDIO_TaskUp\n");
}
#endif
/******************************************************************************
* Function: SDIO_IRQ_Handler
* Desc: SDIO device interrupt service routine
* 1. Read & clean the interrupt status
* 2. Wake up the SDIO task to handle the IRQ event
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
VOID SDIO_IRQ_Handler(
IN VOID *pData
)
{
PHAL_SDIO_ADAPTER pSDIODev = pData;
u16 ISRStatus;
ISRStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS);
DBG_SDIO_INFO("%s:ISRStatus=0x%x\n", __FUNCTION__, ISRStatus);
pSDIODev->IntStatus |= ISRStatus;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, ISRStatus); // clean the ISR
#if !TASK_SCHEDULER_DISABLED
if (ISRStatus & BIT_C2H_DMA_OK) {
SDIO_SetEvent(pSDIODev, SDIO_EVENT_C2H_DMA_DONE);
RtlUpSemaFromISR(&pSDIODev->RxSema);
}
if (ISRStatus & ~BIT_C2H_DMA_OK) {
SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ);
RtlUpSemaFromISR(&pSDIODev->TxSema);
}
#else
SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ|SDIO_EVENT_C2H_DMA_DONE);
SDIO_TaskUp(pSDIODev);
#endif
}
/******************************************************************************
* Function: SDIO_Interrupt_Init
* Desc: SDIO device interrupt initialization.
* 1. Register the ISR
* 2. Initial the IMR register
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
VOID SDIO_Interrupt_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
)
{
IRQ_HANDLE SdioIrqHandle;
pSDIODev->IntMask = BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | BIT_H2C_MSG_INT | BIT_RPWM1_INT | \
BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | BIT_RXBD_FLAG_ERR_INT;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, pSDIODev->IntMask); // Clean pending interrupt first
SdioIrqHandle.Data = (u32) pSDIODev;
SdioIrqHandle.IrqNum = SDIO_DEVICE_IRQ;
SdioIrqHandle.IrqFun = (IRQ_FUN) SDIO_IRQ_Handler;
SdioIrqHandle.Priority = SDIO_IRQ_PRIORITY;
InterruptRegister(&SdioIrqHandle);
InterruptEn(&SdioIrqHandle);
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask);
}
/******************************************************************************
* Function: SDIO_Interrupt_DeInit
* Desc: SDIO device interrupt De-Initial.
* 1. UnRegister the ISR
* 2. Initial the IMR register with 0
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
VOID SDIO_Interrupt_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
)
{
IRQ_HANDLE SdioIrqHandle;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, 0xffff); // Clean pending interrupt first
SdioIrqHandle.Data = (u32) pSDIODev;
SdioIrqHandle.IrqNum = SDIO_DEVICE_IRQ;
SdioIrqHandle.Priority = SDIO_IRQ_PRIORITY;
InterruptDis(&SdioIrqHandle);
InterruptUnRegister(&SdioIrqHandle);
}
/******************************************************************************
* Function: SDIO_Enable_Interrupt
* Desc: SDIO enable interrupt by modify the interrupt mask
*
* Para:
* pSDIODev: The SDIO device data structor.
* IntMask: The bit map to enable the interrupt.
******************************************************************************/
__inline VOID SDIO_Enable_Interrupt(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
)
{
RtlEnterCritical();
pSDIODev->IntMask |= IntMask;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask);
RtlExitCritical();
}
/******************************************************************************
* Function: SDIO_Disable_Interrupt
* Desc: SDIO disable interrupt by modify the interrupt mask
*
* Para:
* pSDIODev: The SDIO device data structor.
* IntMask: The bit map to disable the interrupt.
******************************************************************************/
__inline VOID SDIO_Disable_Interrupt(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
)
{
RtlEnterCritical();
pSDIODev->IntMask &= ~IntMask;
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask);
RtlExitCritical();
}
/******************************************************************************
* Function: SDIO_Clear_ISR
* Desc: SDIO clear ISR bit map.
*
* Para:
* pSDIODev: The SDIO device data structor.
* IntMask: The bit map to be clean.
******************************************************************************/
__inline VOID SDIO_Clear_ISR(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 IntMask
)
{
RtlEnterCritical();
pSDIODev->IntStatus &= ~IntMask;
RtlExitCritical();
}
/******************************************************************************
* Function: SDIO_TxTask
* Desc: The SDIO task handler. This is the main function of the SDIO device
* driver.
* 1. Handle interrupt events.
* * SDIO TX data ready
* * Error handling
* 2.
*
* Para:
* pSDIODev: The SDIO device data structor.
******************************************************************************/
VOID SDIO_TxTask(
IN VOID *pData
)
{
PHAL_SDIO_ADAPTER pSDIODev = pData;
/* Initial resource */
#if !TASK_SCHEDULER_DISABLED
/* enable the interrupt */
SDIO_Interrupt_Init(pSDIODev);
// Update the power state indication
pSDIODev->CCPWM2 = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
pSDIODev->CCPWM2 |= CPWM2_ACT_BIT;
pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT;
HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2);
/* Indicate the Host system that the TX/RX is ready */
HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \
HAL_SDIO_READ8(REG_SPDIO_CPU_IND)|BIT_SYSTEM_TRX_RDY_IND);
#if SDIO_MP_MODE
if (pSDIODev->pPeriodTimer) {
RtlTimerStart(pSDIODev->pPeriodTimer, 0);
}
#endif
#endif
#if !TASK_SCHEDULER_DISABLED
for (;;)