Draft: RISC-V support #829

TobiasFaller · 2020-09-17T22:34:34Z

This will be my attempt to implement RISC-V support (#735) for Pwndbg.
Capstone has RISC-V support only in the next branch, so this pull request will stay open until the new release version 5.0.0 is released.
Feel free to give feedback.

TobiasFaller · 2020-09-18T14:14:52Z

There are currently some bugs in Capstone / the Python bindings.
This should be fixed soon.

See:
capstone-engine/capstone#1690
capstone-engine/capstone#1691

TobiasFaller · 2020-09-18T14:51:15Z

This post has been moved to a separate pull request #830.

pwndbg/regs.py

disconnect3d · 2020-12-14T06:36:56Z

@TobiasFaller there seem to be a conflict; can u fix it soo we can merge it? :)

TobiasFaller · 2020-12-14T08:56:00Z

@TobiasFaller there seem to be a conflict; can u fix it soo we can merge it? :)

Yeah, sure. As this is still a WIP I have not rebased it yet.
I will update this MR after Feb. the 18th.

TobiasFaller · 2021-03-04T10:37:25Z

Updates: capstone-engine/capstone#1690 has now been merged too.

TobiasFaller · 2021-07-19T18:47:08Z

Update: There has not been a release of aquynh/capstone with RISC-V support yet. Maybe it is time to move to a more active project / fork?

disconnect3d · 2021-07-26T23:42:45Z

Maybe it is time to move to a more active project / fork?

Is there actually a fork that is more active or/and supports RISC-V?

lyctw · 2022-03-10T14:04:25Z

Hi
Does RISC-V support still wait for Capstone 5.0.0 release?

TobiasFaller · 2022-03-10T14:08:53Z

Hi Dose RISC-V support still wait for Capstone 5.0.0 release?

Yes, but the first release candidates seem to have been released ten days ago which means it's probably not long before a stable release will be done.

Please keep in mind that this RISC-V extension's code has not been fully tested yet and can only be considered a prototype.
I'll probably get back to this implementation in the next weeks.

disconnect3d · 2022-08-17T21:10:28Z

@TobiasFaller ping :)

TobiasFaller · 2022-08-17T22:09:51Z

@TobiasFaller ping :)

Still waiting for a stable capstone 5.0 release.

lonnywong · 2022-08-24T04:04:49Z

@disconnect3d @TobiasFaller

It's been a long time. Can we support RISC-V without capstone?

How about make a simple disassembler by calling

instr = gdb.execute("x/i %#x" % address, to_string=True)

base on pwndbg#829 by Tobias Faller <faller@endiio.com>

* add riscv:rv64 registers base on #829 by Tobias Faller <faller@endiio.com> * disassemble without capstone to support other architectures * ignore gdb.error on context_backtrace

FantasqueX · 2022-09-14T17:01:39Z

Really want this feature. Encounter some difficulty when debugging on riscv64 hardware without pwndbg. Thanks everyone working on this issue in advance.

Update: I'll try the one in master branch.

disconnect3d · 2022-09-14T17:06:39Z

@FantasqueX pls let me know if and how the dev/latest version works for u!

disconnect3d · 2022-09-14T17:07:25Z

@TobiasFaller fwiw we could potentially use the release candidate version too. I'm rather okay with it, as long as we give a choice to users to switch between the current solution and capstone based one.

TobiasFaller · 2022-09-18T19:25:04Z

@TobiasFaller fwiw we could potentially use the release candidate version too. I'm rather okay with it, as long as we give a choice to users to switch between the current solution and capstone based one.

@disconnect3d Okay, I'll see what I can do and how to make the release candidate version usable. I'll need to validate and rebase the current implementation though, so it will take time.

Xeonacid · 2023-03-21T02:31:27Z

@disconnect3d Okay, I'll see what I can do and how to make the release candidate version usable. I'll need to validate and rebase the current implementation though, so it will take time.

Hi. How is it going? Is there anything I can do to help? I'm very interested in this work.

disconnect3d · 2023-03-21T08:33:17Z

@Xeonacid Hi! Sure, you can help :)

We added some basic support for riscv:rv64 in #1588.

To work with RISC-V further we need to:

Add other RISC-V architecture variants: mainly, make sure we map registers properly and that we have a corresponding Capstone disassebler. If there is no Capstone disassembler, we have to fallback to the GDB one somehow.
Ideally, add some basic qemu tests for those ("does it launch without crash", "does it provide correct registers, disassembly and stack output", etc)
Extend the support to enhance the disassembly: this is what DisassemblyAssistant can be used for. Note that this feature overall may need some overwork as it was mainly designed for x86/x64 stuff.

Generally, I think we should close this draft since it is conflicted and not worked upon anyway, but one can base upon this and extend Pwndbg further.

Xeonacid · 2023-03-21T08:43:11Z

@Xeonacid Hi! Sure, you can help :)

We added some basic support for riscv:rv64 in #1588.

To work with RISC-V further we need to:

Add other RISC-V architecture variants: mainly, make sure we map registers properly and that we have a corresponding Capstone disassebler. If there is no Capstone disassembler, we have to fallback to the GDB one somehow.

Ideally, add some basic qemu tests for those ("does it launch without crash", "does it provide correct registers, disassembly and stack output", etc)

Extend the support to enhance the disassembly: this is what DisassemblyAssistant can be used for. Note that this feature overall may need some overwork as it was mainly designed for x86/x64 stuff.

Generally, I think we should close this draft since it is conflicted and not worked upon anyway, but one can base upon this and extend Pwndbg further.

Thanks for the information! I will work on this.

disconnect3d · 2023-03-21T08:55:44Z

Thanks for the information! I will work on this.

Great! If you have any questions, you can also ask on our Discord: https://discord.gg/9rrbG3yt

disconnect3d · 2023-03-21T08:55:58Z

I am closing this PR for now

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

* Improve RISCV support This is a resurrection of #829 Co-authored-by: Tobias Faller <faller@endiio.com> * Silence bogus vermin warning * Fix relative backwards jump calculations The target address wouldn't be truncated to the pointer size. * Add basic qemu-user test * Run qemu-user tests in CI * Make shfmt happy * Fix pwntools < 4.11.0 support * Support RISCV32 for pwntools < 4.11.0 as well --------- Co-authored-by: Tobias Faller <faller@endiio.com>

disconnect3d reviewed Oct 5, 2020

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TobiasFaller mentioned this pull request Dec 14, 2020

Changed register list to use precomputed tuples #866

Merged

TobiasFaller changed the title ~~[WIP] RISC-V support~~ Draft: RISC-V support Jul 19, 2021

TobiasFaller changed the title ~~Draft: RISC-V support~~ [WIP] RISC-V support Jul 19, 2021

TobiasFaller added 3 commits December 2, 2021 20:45

Added registers for RISC-V

58095a5

Added RISC-V architecture

57aaa5c

Added RISC-V disassembly helper concept

bab21a4

TobiasFaller force-pushed the feature-riscv branch from 1c0455f to bab21a4 Compare December 2, 2021 19:49

Added missing bracket

046d00e

TobiasFaller changed the title ~~[WIP] RISC-V support~~ Draft: RISC-V support Mar 10, 2022

lonnywong added a commit to lonnywong/pwndbg that referenced this pull request Aug 24, 2022

add riscv:rv64 registers

bc137b7

base on pwndbg#829 by Tobias Faller <faller@endiio.com>

lonnywong mentioned this pull request Aug 24, 2022

support riscv:rv64 without capstone #1096

Merged

lonnywong added a commit to lonnywong/pwndbg that referenced this pull request Aug 30, 2022

add riscv:rv64 registers

ef9cad2

base on pwndbg#829 by Tobias Faller <faller@endiio.com>

lonnywong added a commit to lonnywong/pwndbg that referenced this pull request Aug 30, 2022

add riscv:rv64 registers

89ec8df

base on pwndbg#829 by Tobias Faller <faller@endiio.com>

disconnect3d mentioned this pull request Aug 30, 2022

Hope add basic support for RISC-V #735

Closed

disconnect3d mentioned this pull request Feb 22, 2023

Added support for riscv:rv64 #1588

Merged

disconnect3d closed this Mar 21, 2023

peace-maker added a commit to peace-maker/pwndbg that referenced this pull request May 2, 2023

Improve RISCV support

e2c3741

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

peace-maker added a commit to peace-maker/pwndbg that referenced this pull request May 30, 2023

Improve RISCV support

34f6437

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

peace-maker added a commit to peace-maker/pwndbg that referenced this pull request Jun 26, 2023

Improve RISCV support

516b78b

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

peace-maker added a commit to peace-maker/pwndbg that referenced this pull request Jun 26, 2023

Improve RISCV support

1926033

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

peace-maker added a commit to peace-maker/pwndbg that referenced this pull request Jun 26, 2023

Improve RISCV support

45f6ee7

This is a resurrection of pwndbg#829 Co-authored-by: Tobias Faller <faller@endiio.com>

peace-maker mentioned this pull request Jun 26, 2023

Improve RISCV support #1770

Merged

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Draft: RISC-V support #829

Draft: RISC-V support #829

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Draft: RISC-V support #829

Draft: RISC-V support #829

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