Use 1800.2 naming convention for all base classes

Signed-off-by: Raviteja Chatta <crteja@lowrisc.org>

pyuvm/__init__.py

@@ -17,19 +17,19 @@
 # Section 14, 15 (Done as fresh Python design)
 from pyuvm.s14_15_python_sequences import *
 # Section 17, Register enumeration
-from pyuvm.s17_pyuvm_reg_enumerations import *
+from pyuvm.s17_uvm_reg_enumerations import *
 # from pyuvm.s17_register_enumerations import *
 # Section 18
 #from pyuvm.s18_register_model import *
-from pyuvm.s18_pyuvm_reg_block import *
+from pyuvm.s18_uvm_reg_block import *
 from pyuvm.s19_pyvum_reg_field import *
-from pyuvm.s20_pyuvm_reg import *
-from pyuvm.s21_pyuvm_reg_map import *
-from pyuvm.s22_pyuvm_mem import *
-from pyuvm.s23_pyuvm_reg_item import *
-from pyuvm.s24_pyuvm_reg_includes import *
-from pyuvm.s25_pyuvm_adapter import *
-from pyuvm.s26_pyuvm_predictor import *
+from pyuvm.s20_uvm_reg import *
+from pyuvm.s21_uvm_reg_map import *
+from pyuvm.s22_uvm_mem import *
+from pyuvm.s23_uvm_reg_item import *
+from pyuvm.s24_uvm_reg_includes import *
+from pyuvm.s25_uvm_adapter import *
+from pyuvm.s26_uvm_predictor import *
 
 # Extension Modules
 from pyuvm.extension_classes import *

pyuvm/s17_pyuvm_reg_enumerations.py → pyuvm/s17_uvm_reg_enumerations.py

@@ -8,12 +8,12 @@
 PYUVM_REG_ADDR_WIDTH = 64
 
 # 17.2.1.1 uvm_reg_data_t
-pyuvm_reg_data_t = int
+uvm_reg_data_t = int
 
 # 17.2.1.3 uvm_reg_addr_t
-pyuvm_reg_addr_t = int
+uvm_reg_addr_t = int
 
-pyuvm_reg_policy_t = [
+uvm_reg_policy_t = [
     "RO",       # no effect, R: no effect.
     "RW",       # as is, R: no effect.
     "RC",       # no effect, R: clears all bits.
@@ -46,7 +46,7 @@
     "NOACCESS"  # no effect, R: no effect.
 ]
 
-pyuvm_reg_field_ignore_rand_mode = ["RW", "WRC", "WRS", "WO", "W1", "WO1"]
+uvm_reg_field_ignore_rand_mode = ["RW", "WRC", "WRS", "WO", "W1", "WO1"]
 
 
 # 17.2.1.7 uvm_hdl_path_slice

pyuvm/s18_pyuvm_reg_block.py → pyuvm/s18_uvm_reg_block.py

@@ -2,7 +2,7 @@
 # 18.1.1 Class declaration
 
 
-class pyuvm_reg_block(uvm_object):
+class uvm_reg_block(uvm_object):
 
     # 18.1.2.1
     # TODO Fix signature

pyuvm/s19_pyvum_reg_field.py

@@ -1,17 +1,17 @@
 # Main Packages same as import uvm_pkg or uvm_defines.
 from pyuvm import uvm_object
-from pyuvm.s24_pyuvm_reg_includes import *
+from pyuvm.s24_uvm_reg_includes import *
 
 
 # Class declaration for register field
 # @rand_enable(enable_pyvsc)
 
 
-class pyuvm_reg_field(uvm_object):
+class uvm_reg_field(uvm_object):
     # constructor
-    def __init__(self, name='pyuvm_reg_field'):
+    def __init__(self, name='uvm_reg_field'):
         super().__init__(name)
-        self.access_list = pyuvm_reg_policy_t
+        self.access_list = uvm_reg_policy_t
         self._parent = None
         self._size = 0
         self._lsb_pos = None
@@ -30,7 +30,7 @@ def __init__(self, name='pyuvm_reg_field'):
         self._config_done = False
         self._has_been_writ = False
         self._prediction = predict_t
-        self._response = pyuvm_resp_t
+        self._response = uvm_resp_t
         self._name = name
         self._header = name + " -- "
         # These 2 flags cannot change for fields since are part of the parent register
@@ -188,7 +188,7 @@ def get(self):
     def reset(self):
         self._field_mirrored = self._reset
         self._has_been_writ = False
-        self._response = pyuvm_resp_t.PASS_RESP
+        self._response = uvm_resp_t.PASS_RESP
 
     # atomic get value
     def get_value(self):
@@ -208,7 +208,7 @@ def set_access(self, access_value):
                 self._access = "NOACCESS"
 
     # Atomic set response status for fields
-    def set_response(self, f_response: pyuvm_resp_t):
+    def set_response(self, f_response: uvm_resp_t):
         self._response = f_response
 
     # Atomic set prediction type for field. This comes from the register parent
@@ -430,13 +430,13 @@ def predict_response(self, value, path: path_t, direction: access_e):
         # Check the Direction and the access type along with the enable error flags (if error is supposed to be thown then send it out)
         # if we try to write a 1 when the access on write will require the 0 to generate some effect
         if ((direction == access_e.PYUVM_WRITE) & (self.get_access() in ["RO", "RW", "RC", "RS"]) & (path == path_t.FRONTDOOR)):
-            self.set_response(pyuvm_resp_t.PASS_RESP if (self._error_on_write is False) else pyuvm_resp_t.ERROR_RESP)
+            self.set_response(uvm_resp_t.PASS_RESP if (self._error_on_write is False) else uvm_resp_t.ERROR_RESP)
         elif ((direction == access_e.PYUVM_READ) & (self.get_access() in ["WO", "WOC", "WOS", "WO1", "NOACCESS", "W1", "W1T", "W0T", "WC", "WS", "W1C", "W1S", "W0C", "W0S"]) & (path == path_t.FRONTDOOR)):
-            self.set_response(pyuvm_resp_t.PASS_RESP if (self._error_on_read is False) else pyuvm_resp_t.ERROR_RESP)
+            self.set_response(uvm_resp_t.PASS_RESP if (self._error_on_read is False) else uvm_resp_t.ERROR_RESP)
         else:  # This will include the BACKDOOR
-            self.set_response(pyuvm_resp_t.PASS_RESP)
+            self.set_response(uvm_resp_t.PASS_RESP)
 
-    # Main field prediction function to be used to predict mirrored value for pyuvm_fields
+    # Main field prediction function to be used to predict mirrored value for uvm_fields
     def field_predict(self, value, path: path_t, direction: access_e):
         # Predict the status based on the flags
         self.predict_response(value, path, direction)
@@ -448,12 +448,12 @@ def field_predict(self, value, path: path_t, direction: access_e):
             self.predict_based_on_read(value)
         elif (path == path_t.BACKDOOR):
             self._field_mirrored = value
-            self.set_response(pyuvm_resp_t.PASS_RESP)
+            self.set_response(uvm_resp_t.PASS_RESP)
         else:
             self._add_error(uvm_reg_field_error_decoder.WRONG_COMBINATION_PREDICTION_DIRECTION)
-            error_out(self._header, "Wrong combination of PATH - PREDICTION TYPE and DIRECTION on pyuvm_field -- field_predict function")
+            error_out(self._header, "Wrong combination of PATH - PREDICTION TYPE and DIRECTION on uvm_field -- field_predict function")
 
-    # String representation of pyuvm_reg_filed class content
+    # String representation of uvm_reg_filed class content
     def __str__(self) -> str:
         return f"   {self._header} \
                     parent :    {self._parent} \

pyuvm/s20_pyuvm_reg.py → pyuvm/s20_uvm_reg.py

@@ -1,13 +1,13 @@
 # Main Packages same as import uvm_pkg or uvm_defines.svh
 from pyuvm import uvm_object
-from pyuvm.s18_pyuvm_reg_block import *
-from pyuvm.s21_pyuvm_reg_map import pyuvm_reg_map
-from pyuvm.s24_pyuvm_reg_includes import *
+from pyuvm.s18_uvm_reg_block import *
+from pyuvm.s21_uvm_reg_map import uvm_reg_map
+from pyuvm.s24_uvm_reg_includes import *
 
 
-class pyuvm_reg(uvm_object):
+class uvm_reg(uvm_object):
     # Constructor
-    def __init__(self, name="pyuvm_reg", reg_width=32):
+    def __init__(self, name="uvm_reg", reg_width=32):
         super().__init__(name)
         self._parent = None
         self._fields = []
@@ -30,7 +30,7 @@ def __init__(self, name="pyuvm_reg", reg_width=32):
         self._op_in_progress = False
 
     # configure
-    def configure(self, parent: pyuvm_reg_block, address, hdl_path, throw_error_on_read=False, throw_error_on_write=False):
+    def configure(self, parent: uvm_reg_block, address, hdl_path, throw_error_on_read=False, throw_error_on_write=False):
         self._parent = parent
         self._address = address
         self._path = hdl_path
@@ -161,12 +161,12 @@ def build(self):
         pass
 
     # Write Method (TASK)
-    async def write(self, value, map: pyuvm_reg_map, path: path_t, check: check_t) -> pyuvm_resp_t:
+    async def write(self, value, map: uvm_reg_map, path: path_t, check: check_t) -> uvm_resp_t:
         # This Task should implement the main read method via only FRONTDOOR
         # TODO: BACKDOOT and USER FRONTDOOR are missing
         # This Task returns only the operation status
         # Local Variables to be returned
-        status = pyuvm_resp_t
+        status = uvm_resp_t
         # Given the map we do not check if the current register exists in the map
         # (redundant check) since the register is directly taken from the MAP
         # We check instead if the map is set and if only one exists (multiple access)
@@ -185,18 +185,18 @@ async def write(self, value, map: pyuvm_reg_map, path: path_t, check: check_t) -
                 error_out(self._header, "WRITE: map cannot be NULL")
             self._op_in_progress = False
         else:
-            raise UVMFatalError("pyuvm_reg -- write -- cannot perform an operation while another is in progress")
+            raise UVMFatalError("uvm_reg -- write -- cannot perform an operation while another is in progress")
         # Return from Task
         return status
 
     # Read Method (TASK)
-    async def read(self, map: pyuvm_reg_map, path: path_t, check: check_t):
+    async def read(self, map: uvm_reg_map, path: path_t, check: check_t):
         # This Task should implement the main read method via only FRONTDOOR
         # TODO: BACKDOOT and USER FRONTDOOR are missing
         # This Task returns only the operation status and the read value
         # (0 is status is error)
         # Local Variables to be returned
-        status = pyuvm_resp_t
+        status = uvm_resp_t
         # Given the map we do not check if the current register exists in the map
         # (redundant check) since the register is directly taken from the MAP
         # We check instead if the map is set and if only one exists (multiple access)
@@ -208,12 +208,12 @@ async def read(self, map: pyuvm_reg_map, path: path_t, check: check_t):
             self._op_in_progress = True
             if map is not None:
                 status, read_data = await map.process_read_operation(self.get_address(), path, check)
-                if status == pyuvm_resp_t.ERROR_RESP:
+                if status == uvm_resp_t.ERROR_RESP:
                     read_data = 0
             else:
                 error_out(self._header, "READ: map cannot be NULL")
             self._op_in_progress = False
         else:
-            raise UVMFatalError("pyuvm_reg -- read -- cannot perform an operation while another is in progress")
+            raise UVMFatalError("uvm_reg -- read -- cannot perform an operation while another is in progress")
         # Return from Task
         return status, read_data

pyuvm/s21_pyuvm_reg_map.py → pyuvm/s21_uvm_reg_map.py

@@ -1,15 +1,15 @@
 # Import Main Packages
 from pyuvm import uvm_object, uvm_sequencer
-from pyuvm.s24_pyuvm_reg_includes import *
-from pyuvm.s25_pyuvm_adapter import *
-from pyuvm.s26_pyuvm_predictor import *
-from pyuvm.s18_pyuvm_reg_block import *
+from pyuvm.s24_uvm_reg_includes import *
+from pyuvm.s25_uvm_adapter import *
+from pyuvm.s26_uvm_predictor import *
+from pyuvm.s18_uvm_reg_block import *
 
 
 # Class declaration: uvm_reg_map
-class pyuvm_reg_map(uvm_object):
+class uvm_reg_map(uvm_object):
     # Constructor
-    def __init__(self, name="pyuvm_reg_map"):
+    def __init__(self, name="uvm_reg_map"):
         super().__init__(name)
         self._parent = None
         self._base_addr = None
@@ -18,12 +18,12 @@ def __init__(self, name="pyuvm_reg_map"):
         self.header = name + " -- "
 
     # Function called by the REG_BLOCK create_map funcction
-    # the parent value here should be a pyuvm_reg_block instance type
+    # the parent value here should be a uvm_reg_block instance type
     def configure(self, parent, base_addr):
-        if (isinstance(parent, pyuvm_reg_block)):
+        if (isinstance(parent, uvm_reg_block)):
             self._parent = parent
         else:
-            UVMFatalError("pyuvm_reg_map -- configure -- parent should be pyuvm_reg_block type")
+            UVMFatalError("uvm_reg_map -- configure -- parent should be uvm_reg_block type")
         self._base_addr = base_addr
         # No support for Byte_Addressing nor for Byte_en TODO: add
 
@@ -49,7 +49,7 @@ def get_reg_by_offset(self, offset):
 
     # set_predictor
     def set_predictor(self, predictor):
-        if isinstance(predictor, pyuvm_reg_predictor):
+        if isinstance(predictor, uvm_reg_predictor):
             self.predictor = predictor
         else:
             error_out(self.header, "predictor should be type of uvm_reg_predictor")
@@ -63,7 +63,7 @@ def get_predictor(self):
 
     # set_adapter
     def set_adapter(self, adapter):
-        if isinstance(adapter, pyuvm_reg_adapter):
+        if isinstance(adapter, uvm_reg_adapter):
             self.adapter = adapter
         else:
             error_out(self.header, "adapter should be type of uvm_reg_adapter")

pyuvm/s22_pyuvm_mem.py → pyuvm/s22_uvm_mem.py

@@ -4,5 +4,5 @@
 
 
 # Pyuvm Mem Class declaration abstraction
-class pyuvm_mem(uvm_object):
+class uvm_mem(uvm_object):
     pass

pyuvm/s23_pyuvm_reg_item.py → pyuvm/s23_uvm_reg_item.py

@@ -1,12 +1,12 @@
 # Import Main Package
 from pyuvm import uvm_sequence_item
 from pyuvm import uvm_object
-from pyuvm.s24_pyuvm_reg_includes import *
+from pyuvm.s24_uvm_reg_includes import *
 
 
 # Main Class
 # @rand_enable(enable_pyvsc,uvm_sequence_item)
-class pyuvm_reg_item(uvm_sequence_item):
+class uvm_reg_item(uvm_sequence_item):
     # constructor
     def __init__(self, name='item'):
         # Kind of element being accessed: REG, MEM, or FIELD. See <uvm_elem_kind_e>.

pyuvm/s24_pyuvm_reg_includes.py → pyuvm/s24_uvm_reg_includes.py

@@ -6,7 +6,7 @@
 #import vsc
 import copy
 from pyuvm.error_classes import UVMFatalError, UVMError
-from pyuvm.s17_pyuvm_reg_enumerations import *
+from pyuvm.s17_uvm_reg_enumerations import *
 
 class path_t(Enum):
     '''
@@ -56,9 +56,9 @@ class access_e(Enum):
     PYUVM_READ  = 0
     PYUVM_WRITE = 1
 
-class pyuvm_resp_t(Enum):
+class uvm_resp_t(Enum):
     '''
-    pyuvm_resp_t is the main response based on the access issued
+    uvm_resp_t is the main response based on the access issued
     PASS_RESP  = 0
     ERROR_RESP = 1
     '''
@@ -114,7 +114,7 @@ class uvm_reg_bus_op:
     data:       int
     n_bits:     int
     byte_en:    bool
-    status:     pyuvm_resp_t
+    status:     uvm_resp_t
 
 class uvm_reg_error_decoder(Enum):
     '''

pyuvm/s25_pyuvm_adapter.py → pyuvm/s25_uvm_adapter.py

@@ -2,13 +2,13 @@
 from pyuvm import uvm_object
 from pyuvm import uvm_sequence_item
 from pyuvm import uvm_sequence
-from pyuvm.s24_pyuvm_reg_includes import *
-from pyuvm.s23_pyuvm_reg_item import *
+from pyuvm.s24_uvm_reg_includes import *
+from pyuvm.s23_uvm_reg_item import *
 
 ## Main Class
-class pyuvm_reg_adapter(uvm_object):
+class uvm_reg_adapter(uvm_object):
     ## Constructor
-    def __init__(self, name="pyuvm_reg_adapter"):
+    def __init__(self, name="uvm_reg_adapter"):
         super().__init__(name)
         #    Set this bit in extensions of this class if the bus protocol supports
         #    byte enables.
@@ -41,7 +41,7 @@ def get_item(self):
         return self.reg_item
 
     # Use this method to set the item into the adapter class
-    def set_item(self, item: pyuvm_reg_item):
+    def set_item(self, item: uvm_reg_item):
         self.reg_item = item
 
     # Use this method to set the parent sequence into the adapter class 

pyuvm/s26_pyuvm_predictor.py → pyuvm/s26_uvm_predictor.py

@@ -2,11 +2,11 @@
 from pyuvm import uvm_object
 from pyuvm import uvm_sequence_item
 from pyuvm import uvm_sequence
-from pyuvm.s24_pyuvm_reg_includes import *
-from pyuvm.s23_pyuvm_reg_item import *
+from pyuvm.s24_uvm_reg_includes import *
+from pyuvm.s23_uvm_reg_item import *
 
 ## Main Class
-class pyuvm_reg_predictor(uvm_object):
+class uvm_reg_predictor(uvm_object):
     ## Constructor
-    def __init__(self, name="pyuvm_reg_predictor"):
+    def __init__(self, name="uvm_reg_predictor"):
         super().__init__(name)