Regenerate reg block using peakrdl-verilog #173
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This PR failed due to conflicts, perhaps with #171 |
- Regenerated regblock from rdl file using peakrdl-verilog - This implementation doesnt use structures that were unsupported in icarus and verilator - Also, the reg block interface is now a simple handshake interface similar to APB but without sel and enable signals - for sake of simplicity, register field write enable bits are always driven with 1 Signed-off-by: Raviteja Chatta <crteja@lowrisc.org>
Earlier implementation had clock toggling in tinyalu.sv Use cocotb Clock to generate clock in test run_phase Signed-off-by: Raviteja Chatta <crteja@lowrisc.org>
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- Add dummy reb block and a uvm_agent to drive register interface from testbench - Fix errors with method signatures - Fix errors with creation of default map - Update bus2reg to return uvm_reg_op Signed-off-by: Raviteja Chatta <crteja@lowrisc.org>
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icarusandverilatorselandenablesignalsAssuming this module now compiles with all EDA tools since it compiles and runs with
icarusandverilator