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q3kmips

The little MIPS that couldn't.

What is it?

It's a classic-pipeline, hand-crafted, partial MIPS32 implementation. It probably doesn't hold any intristic value, as it's a way for me to learn computer architecture from the ground up.

See pipeline.grphml for a yEd diagram of what this whole thing looks like.

Is it any good?

Not yet, really. It's a work in progress - the Fetch and ICache modules seem to be working and are tested. The decode stage is in progress, the rest is planned.

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A toy MIPS pipelined CPU in Verilog.

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