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util: Extract flush_icache_range to cacheflush.c
This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Original file line number | Diff line number | Diff line change |
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/* | ||
* Flush the host cpu caches. | ||
* | ||
* This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
* See the COPYING file in the top-level directory. | ||
*/ | ||
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#ifndef QEMU_CACHEFLUSH_H | ||
#define QEMU_CACHEFLUSH_H | ||
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) | ||
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static inline void flush_icache_range(uintptr_t start, uintptr_t stop) | ||
{ | ||
/* icache is coherent and does not require flushing. */ | ||
} | ||
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#else | ||
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void flush_icache_range(uintptr_t start, uintptr_t stop); | ||
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#endif | ||
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#endif /* QEMU_CACHEFLUSH_H */ |
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Original file line number | Diff line number | Diff line change |
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/* | ||
* Flush the host cpu caches. | ||
* | ||
* This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
* See the COPYING file in the top-level directory. | ||
*/ | ||
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#include "qemu/osdep.h" | ||
#include "qemu/cacheflush.h" | ||
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) | ||
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/* Caches are coherent and do not require flushing; symbol inline. */ | ||
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#elif defined(__mips__) | ||
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#ifdef __OpenBSD__ | ||
#include <machine/sysarch.h> | ||
#else | ||
#include <sys/cachectl.h> | ||
#endif | ||
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void flush_icache_range(uintptr_t start, uintptr_t stop) | ||
{ | ||
cacheflush((void *)start, stop - start, ICACHE); | ||
} | ||
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#elif defined(__powerpc__) | ||
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void flush_icache_range(uintptr_t start, uintptr_t stop) | ||
{ | ||
uintptr_t p, start1, stop1; | ||
size_t dsize = qemu_dcache_linesize; | ||
size_t isize = qemu_icache_linesize; | ||
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start1 = start & ~(dsize - 1); | ||
stop1 = (stop + dsize - 1) & ~(dsize - 1); | ||
for (p = start1; p < stop1; p += dsize) { | ||
asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); | ||
} | ||
asm volatile ("sync" : : : "memory"); | ||
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start &= start & ~(isize - 1); | ||
stop1 = (stop + isize - 1) & ~(isize - 1); | ||
for (p = start1; p < stop1; p += isize) { | ||
asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); | ||
} | ||
asm volatile ("sync" : : : "memory"); | ||
asm volatile ("isync" : : : "memory"); | ||
} | ||
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#elif defined(__sparc__) | ||
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void flush_icache_range(uintptr_t start, uintptr_t stop) | ||
{ | ||
uintptr_t p; | ||
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for (p = start & -8; p < ((stop + 7) & -8); p += 8) { | ||
__asm__ __volatile__("flush\t%0" : : "r" (p)); | ||
} | ||
} | ||
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#else | ||
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void flush_icache_range(uintptr_t start, uintptr_t stop) | ||
{ | ||
__builtin___clear_cache((char *)start, (char *)stop); | ||
} | ||
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#endif |
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