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target/loongarch: Implement vbitclr vbitset vbitrev
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This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-32-gaosong@loongson.cn>
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@gaosong-loongson
gaosong-loongson committed May 6, 2023
1 parent bb22ee5 commit 0b1e670
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25 changes: 25 additions & 0 deletions target/loongarch/disas.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1272,3 +1272,28 @@ INSN_LSX(vpcnt_b, vv)
INSN_LSX(vpcnt_h, vv)
INSN_LSX(vpcnt_w, vv)
INSN_LSX(vpcnt_d, vv)

INSN_LSX(vbitclr_b, vvv)
INSN_LSX(vbitclr_h, vvv)
INSN_LSX(vbitclr_w, vvv)
INSN_LSX(vbitclr_d, vvv)
INSN_LSX(vbitclri_b, vv_i)
INSN_LSX(vbitclri_h, vv_i)
INSN_LSX(vbitclri_w, vv_i)
INSN_LSX(vbitclri_d, vv_i)
INSN_LSX(vbitset_b, vvv)
INSN_LSX(vbitset_h, vvv)
INSN_LSX(vbitset_w, vvv)
INSN_LSX(vbitset_d, vvv)
INSN_LSX(vbitseti_b, vv_i)
INSN_LSX(vbitseti_h, vv_i)
INSN_LSX(vbitseti_w, vv_i)
INSN_LSX(vbitseti_d, vv_i)
INSN_LSX(vbitrev_b, vvv)
INSN_LSX(vbitrev_h, vvv)
INSN_LSX(vbitrev_w, vvv)
INSN_LSX(vbitrev_d, vvv)
INSN_LSX(vbitrevi_b, vv_i)
INSN_LSX(vbitrevi_h, vv_i)
INSN_LSX(vbitrevi_w, vv_i)
INSN_LSX(vbitrevi_d, vv_i)
27 changes: 27 additions & 0 deletions target/loongarch/helper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -485,3 +485,30 @@ DEF_HELPER_3(vpcnt_b, void, env, i32, i32)
DEF_HELPER_3(vpcnt_h, void, env, i32, i32)
DEF_HELPER_3(vpcnt_w, void, env, i32, i32)
DEF_HELPER_3(vpcnt_d, void, env, i32, i32)

DEF_HELPER_FLAGS_4(vbitclr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclr_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclr_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitclri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitclri_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitclri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

DEF_HELPER_FLAGS_4(vbitset_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitset_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitset_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitset_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitseti_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitseti_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitseti_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitseti_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

DEF_HELPER_FLAGS_4(vbitrev_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitrev_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitrev_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitrev_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitrevi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitrevi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitrevi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitrevi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
305 changes: 305 additions & 0 deletions target/loongarch/insn_trans/trans_lsx.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -3111,3 +3111,308 @@ TRANS(vpcnt_b, gen_vv, gen_helper_vpcnt_b)
TRANS(vpcnt_h, gen_vv, gen_helper_vpcnt_h)
TRANS(vpcnt_w, gen_vv, gen_helper_vpcnt_w)
TRANS(vpcnt_d, gen_vv, gen_helper_vpcnt_d)

static void do_vbit(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
{
TCGv_vec mask, lsh, t1, one;

lsh = tcg_temp_new_vec_matching(t);
t1 = tcg_temp_new_vec_matching(t);
mask = tcg_constant_vec_matching(t, vece, (8 << vece) - 1);
one = tcg_constant_vec_matching(t, vece, 1);

tcg_gen_and_vec(vece, lsh, b, mask);
tcg_gen_shlv_vec(vece, t1, one, lsh);
func(vece, t, a, t1);
}

static void gen_vbitclr(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
do_vbit(vece, t, a, b, tcg_gen_andc_vec);
}

static void gen_vbitset(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
do_vbit(vece, t, a, b, tcg_gen_or_vec);
}

static void gen_vbitrev(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
do_vbit(vece, t, a, b, tcg_gen_xor_vec);
}

static void do_vbitclr(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shlv_vec, INDEX_op_andc_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vbitclr,
.fno = gen_helper_vbitclr_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitclr,
.fno = gen_helper_vbitclr_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitclr,
.fno = gen_helper_vbitclr_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitclr,
.fno = gen_helper_vbitclr_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}

TRANS(vbitclr_b, gvec_vvv, MO_8, do_vbitclr)
TRANS(vbitclr_h, gvec_vvv, MO_16, do_vbitclr)
TRANS(vbitclr_w, gvec_vvv, MO_32, do_vbitclr)
TRANS(vbitclr_d, gvec_vvv, MO_64, do_vbitclr)

static void do_vbiti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm,
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
{
int lsh;
TCGv_vec t1, one;

lsh = imm & ((8 << vece) -1);
t1 = tcg_temp_new_vec_matching(t);
one = tcg_constant_vec_matching(t, vece, 1);

tcg_gen_shli_vec(vece, t1, one, lsh);
func(vece, t, a, t1);
}

static void gen_vbitclri(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
{
do_vbiti(vece, t, a, imm, tcg_gen_andc_vec);
}

static void gen_vbitseti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
{
do_vbiti(vece, t, a, imm, tcg_gen_or_vec);
}

static void gen_vbitrevi(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
{
do_vbiti(vece, t, a, imm, tcg_gen_xor_vec);
}

static void do_vbitclri(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
int64_t imm, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shli_vec, INDEX_op_andc_vec, 0
};
static const GVecGen2i op[4] = {
{
.fniv = gen_vbitclri,
.fnoi = gen_helper_vbitclri_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitclri,
.fnoi = gen_helper_vbitclri_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitclri,
.fnoi = gen_helper_vbitclri_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitclri,
.fnoi = gen_helper_vbitclri_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
}

TRANS(vbitclri_b, gvec_vv_i, MO_8, do_vbitclri)
TRANS(vbitclri_h, gvec_vv_i, MO_16, do_vbitclri)
TRANS(vbitclri_w, gvec_vv_i, MO_32, do_vbitclri)
TRANS(vbitclri_d, gvec_vv_i, MO_64, do_vbitclri)

static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shlv_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vbitset,
.fno = gen_helper_vbitset_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitset,
.fno = gen_helper_vbitset_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitset,
.fno = gen_helper_vbitset_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitset,
.fno = gen_helper_vbitset_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}

TRANS(vbitset_b, gvec_vvv, MO_8, do_vbitset)
TRANS(vbitset_h, gvec_vvv, MO_16, do_vbitset)
TRANS(vbitset_w, gvec_vvv, MO_32, do_vbitset)
TRANS(vbitset_d, gvec_vvv, MO_64, do_vbitset)

static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
int64_t imm, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shli_vec, 0
};
static const GVecGen2i op[4] = {
{
.fniv = gen_vbitseti,
.fnoi = gen_helper_vbitseti_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitseti,
.fnoi = gen_helper_vbitseti_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitseti,
.fnoi = gen_helper_vbitseti_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitseti,
.fnoi = gen_helper_vbitseti_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
}

TRANS(vbitseti_b, gvec_vv_i, MO_8, do_vbitseti)
TRANS(vbitseti_h, gvec_vv_i, MO_16, do_vbitseti)
TRANS(vbitseti_w, gvec_vv_i, MO_32, do_vbitseti)
TRANS(vbitseti_d, gvec_vv_i, MO_64, do_vbitseti)

static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shlv_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vbitrev,
.fno = gen_helper_vbitrev_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitrev,
.fno = gen_helper_vbitrev_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitrev,
.fno = gen_helper_vbitrev_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitrev,
.fno = gen_helper_vbitrev_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}

TRANS(vbitrev_b, gvec_vvv, MO_8, do_vbitrev)
TRANS(vbitrev_h, gvec_vvv, MO_16, do_vbitrev)
TRANS(vbitrev_w, gvec_vvv, MO_32, do_vbitrev)
TRANS(vbitrev_d, gvec_vvv, MO_64, do_vbitrev)

static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
int64_t imm, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shli_vec, 0
};
static const GVecGen2i op[4] = {
{
.fniv = gen_vbitrevi,
.fnoi = gen_helper_vbitrevi_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vbitrevi,
.fnoi = gen_helper_vbitrevi_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vbitrevi,
.fnoi = gen_helper_vbitrevi_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vbitrevi,
.fnoi = gen_helper_vbitrevi_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};

tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
}

TRANS(vbitrevi_b, gvec_vv_i, MO_8, do_vbitrevi)
TRANS(vbitrevi_h, gvec_vv_i, MO_16, do_vbitrevi)
TRANS(vbitrevi_w, gvec_vv_i, MO_32, do_vbitrevi)
TRANS(vbitrevi_d, gvec_vv_i, MO_64, do_vbitrevi)
25 changes: 25 additions & 0 deletions target/loongarch/insns.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -973,3 +973,28 @@ vpcnt_b 0111 00101001 11000 01000 ..... ..... @vv
vpcnt_h 0111 00101001 11000 01001 ..... ..... @vv
vpcnt_w 0111 00101001 11000 01010 ..... ..... @vv
vpcnt_d 0111 00101001 11000 01011 ..... ..... @vv

vbitclr_b 0111 00010000 11000 ..... ..... ..... @vvv
vbitclr_h 0111 00010000 11001 ..... ..... ..... @vvv
vbitclr_w 0111 00010000 11010 ..... ..... ..... @vvv
vbitclr_d 0111 00010000 11011 ..... ..... ..... @vvv
vbitclri_b 0111 00110001 00000 01 ... ..... ..... @vv_ui3
vbitclri_h 0111 00110001 00000 1 .... ..... ..... @vv_ui4
vbitclri_w 0111 00110001 00001 ..... ..... ..... @vv_ui5
vbitclri_d 0111 00110001 0001 ...... ..... ..... @vv_ui6
vbitset_b 0111 00010000 11100 ..... ..... ..... @vvv
vbitset_h 0111 00010000 11101 ..... ..... ..... @vvv
vbitset_w 0111 00010000 11110 ..... ..... ..... @vvv
vbitset_d 0111 00010000 11111 ..... ..... ..... @vvv
vbitseti_b 0111 00110001 01000 01 ... ..... ..... @vv_ui3
vbitseti_h 0111 00110001 01000 1 .... ..... ..... @vv_ui4
vbitseti_w 0111 00110001 01001 ..... ..... ..... @vv_ui5
vbitseti_d 0111 00110001 0101 ...... ..... ..... @vv_ui6
vbitrev_b 0111 00010001 00000 ..... ..... ..... @vvv
vbitrev_h 0111 00010001 00001 ..... ..... ..... @vvv
vbitrev_w 0111 00010001 00010 ..... ..... ..... @vvv
vbitrev_d 0111 00010001 00011 ..... ..... ..... @vvv
vbitrevi_b 0111 00110001 10000 01 ... ..... ..... @vv_ui3
vbitrevi_h 0111 00110001 10000 1 .... ..... ..... @vv_ui4
vbitrevi_w 0111 00110001 10001 ..... ..... ..... @vv_ui5
vbitrevi_d 0111 00110001 1001 ...... ..... ..... @vv_ui6

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