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target/riscv: rename ext_ifencei to ext_zifencei
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Add a leading 'z' to improve grepping. When one wants to search for uses
of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i
ifencei'.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@danielhb @alistair23
danielhb authored and alistair23 committed Nov 7, 2023
1 parent 3e01f11 commit 12b12a1
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Showing 4 changed files with 17 additions and 17 deletions.
22 changes: 11 additions & 11 deletions target/riscv/cpu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
Expand Down Expand Up @@ -382,7 +382,7 @@ static void riscv_any_cpu_init(Object *obj)
env->priv_ver = PRIV_VERSION_LATEST;

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
Expand Down Expand Up @@ -430,7 +430,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
#endif

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
Expand All @@ -448,7 +448,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
#endif

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
Expand Down Expand Up @@ -494,7 +494,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)

/* Enable ISA extensions */
cpu->cfg.mmu = true;
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
cpu->cfg.ext_icbom = true;
Expand Down Expand Up @@ -566,7 +566,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
#endif

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
Expand All @@ -584,7 +584,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
#endif

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
Expand All @@ -602,7 +602,7 @@ static void rv32_ibex_cpu_init(Object *obj)
cpu->cfg.epmp = true;

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
Expand All @@ -619,7 +619,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
#endif

/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_zifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
Expand Down Expand Up @@ -1242,7 +1242,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
Expand Down Expand Up @@ -1347,7 +1347,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {

/* Deprecated entries marked for future removal */
const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
Expand Down
2 changes: 1 addition & 1 deletion target/riscv/cpu_cfg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ struct RISCVCPUConfig {
bool ext_zksed;
bool ext_zksh;
bool ext_zkt;
bool ext_ifencei;
bool ext_zifencei;
bool ext_icsr;
bool ext_icbom;
bool ext_icboz;
Expand Down
2 changes: 1 addition & 1 deletion target/riscv/insn_trans/trans_rvi.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -799,7 +799,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)

static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
{
if (!ctx->cfg_ptr->ext_ifencei) {
if (!ctx->cfg_ptr->ext_zifencei) {
return false;
}

Expand Down
8 changes: 4 additions & 4 deletions target/riscv/tcg/tcg-cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -278,23 +278,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
!(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {

if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
!cpu->cfg.ext_icsr) {
error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
return;
}

if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
!cpu->cfg.ext_ifencei) {
if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) &&
!cpu->cfg.ext_zifencei) {
error_setg(errp, "RVG requires Zifencei but user set "
"Zifencei to false");
return;
}

cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);

env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
Expand Down

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