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target/xtensa: add internal/noop SRs and opcodes
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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