Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
- Loading branch information
1 parent
0f4fcf1
commit 249ad85
Showing
7 changed files
with
106 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,73 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
/* | ||
* QEMU Loongson 7A1000 msi interrupt controller. | ||
* | ||
* Copyright (C) 2021 Loongson Technology Corporation Limited | ||
*/ | ||
|
||
#include "qemu/osdep.h" | ||
#include "hw/sysbus.h" | ||
#include "hw/irq.h" | ||
#include "hw/intc/loongarch_pch_msi.h" | ||
#include "hw/intc/loongarch_pch_pic.h" | ||
#include "hw/pci/msi.h" | ||
#include "hw/misc/unimp.h" | ||
#include "migration/vmstate.h" | ||
#include "trace.h" | ||
|
||
static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned size) | ||
{ | ||
return 0; | ||
} | ||
|
||
static void loongarch_msi_mem_write(void *opaque, hwaddr addr, | ||
uint64_t val, unsigned size) | ||
{ | ||
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque); | ||
int irq_num = val & 0xff; | ||
|
||
trace_loongarch_msi_set_irq(irq_num); | ||
assert(irq_num < PCH_MSI_IRQ_NUM); | ||
qemu_set_irq(s->pch_msi_irq[irq_num], 1); | ||
} | ||
|
||
static const MemoryRegionOps loongarch_pch_msi_ops = { | ||
.read = loongarch_msi_mem_read, | ||
.write = loongarch_msi_mem_write, | ||
.endianness = DEVICE_LITTLE_ENDIAN, | ||
}; | ||
|
||
static void pch_msi_irq_handler(void *opaque, int irq, int level) | ||
{ | ||
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(opaque); | ||
|
||
qemu_set_irq(s->pch_msi_irq[irq], level); | ||
} | ||
|
||
static void loongarch_pch_msi_init(Object *obj) | ||
{ | ||
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj); | ||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
|
||
memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops, | ||
s, TYPE_LOONGARCH_PCH_MSI, 0x8); | ||
sysbus_init_mmio(sbd, &s->msi_mmio); | ||
msi_nonbroken = true; | ||
|
||
qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM); | ||
qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM); | ||
} | ||
|
||
static const TypeInfo loongarch_pch_msi_info = { | ||
.name = TYPE_LOONGARCH_PCH_MSI, | ||
.parent = TYPE_SYS_BUS_DEVICE, | ||
.instance_size = sizeof(LoongArchPCHMSI), | ||
.instance_init = loongarch_pch_msi_init, | ||
}; | ||
|
||
static void loongarch_pch_msi_register_types(void) | ||
{ | ||
type_register_static(&loongarch_pch_msi_info); | ||
} | ||
|
||
type_init(loongarch_pch_msi_register_types) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,20 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
/* | ||
* LoongArch 7A1000 I/O interrupt controller definitions | ||
* | ||
* Copyright (C) 2021 Loongson Technology Corporation Limited | ||
*/ | ||
|
||
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" | ||
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) | ||
|
||
/* Msi irq start start from 64 to 255 */ | ||
#define PCH_MSI_IRQ_START 64 | ||
#define PCH_MSI_IRQ_END 255 | ||
#define PCH_MSI_IRQ_NUM 192 | ||
|
||
struct LoongArchPCHMSI { | ||
SysBusDevice parent_obj; | ||
qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM]; | ||
MemoryRegion msi_mmio; | ||
}; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters