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…015-06-03' into staging

trivial patches for 2015-06-03

# gpg: Signature made Wed Jun  3 14:07:47 2015 BST using RSA key ID A4C3D7DB
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"

* remotes/mjt/tags/pull-trivial-patches-2015-06-03: (30 commits)
  configure: postfix --extra-cflags to QEMU_CFLAGS
  cadence_gem: Fix Rx buffer size field mask
  slirp: use less predictable directory name in /tmp for smb config (CVE-2015-4037)
  translate-all: delete prototype for non-existent function
  Add -incoming help text
  hw/display/tc6393xb.c: Fix misusing qemu_allocate_irqs for single irq
  hw/arm/nseries.c: Fix misusing qemu_allocate_irqs for single irq
  hw/alpha/typhoon.c: Fix misusing qemu_allocate_irqs for single irq
  hw/unicore32/puv3.c: Fix misusing qemu_allocate_irqs for single irq
  hw/lm32/milkymist.c: Fix misusing qemu_allocate_irqs for single irq
  hw/lm32/lm32_boards.c: Fix misusing qemu_allocate_irqs for single irq
  hw/ppc/prep.c: Fix misusing qemu_allocate_irqs for single irq
  hw/sparc/sun4m.c: Fix misusing qemu_allocate_irqs for single irq
  hw/timer/arm_timer.c: Fix misusing qemu_allocate_irqs for single irq
  hw/isa/i82378.c: Fix misusing qemu_allocate_irqs for single irq
  hw/isa/lpc_ich9.c: Fix misusing qemu_allocate_irqs for single irq
  hw/i386/pc: Fix misusing qemu_allocate_irqs for single irq
  hw/intc/exynos4210_gic.c: Fix memory leak by adjusting order
  hw/arm/omap_sx1.c: Fix memory leak spotted by valgrind
  hw/ppc/e500.c: Fix memory leak
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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pm215 committed Jun 4, 2015
2 parents 6fa6b31 + de38528 commit 2700a97
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Showing 34 changed files with 71 additions and 86 deletions.
2 changes: 2 additions & 0 deletions Makefile.objs
Expand Up @@ -76,6 +76,8 @@ common-obj-$(CONFIG_SECCOMP) += qemu-seccomp.o

common-obj-$(CONFIG_SMARTCARD_NSS) += $(libcacard-y)

common-obj-$(CONFIG_FDT) += device_tree.o

######################################################################
# qapi

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1 change: 0 additions & 1 deletion Makefile.target
Expand Up @@ -129,7 +129,6 @@ ifdef CONFIG_SOFTMMU
obj-y += arch_init.o cpus.o monitor.o gdbstub.o balloon.o ioport.o numa.o
obj-y += qtest.o bootdevice.o
obj-y += hw/
obj-$(CONFIG_FDT) += device_tree.o
obj-$(CONFIG_KVM) += kvm-all.o
obj-y += memory.o savevm.o cputlb.o
obj-y += memory_mapping.o
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7 changes: 0 additions & 7 deletions block/iscsi.c
Expand Up @@ -1323,13 +1323,6 @@ static int iscsi_open(BlockDriverState *bs, QDict *options, int flags,
const char *filename;
int i, ret = 0;

if ((BDRV_SECTOR_SIZE % 512) != 0) {
error_setg(errp, "iSCSI: Invalid BDRV_SECTOR_SIZE. "
"BDRV_SECTOR_SIZE(%lld) is not a multiple "
"of 512", BDRV_SECTOR_SIZE);
return -EINVAL;
}

opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort);
qemu_opts_absorb_qdict(opts, options, &local_err);
if (local_err) {
Expand Down
2 changes: 1 addition & 1 deletion configure
Expand Up @@ -353,7 +353,7 @@ for opt do
;;
--cpu=*) cpu="$optarg"
;;
--extra-cflags=*) QEMU_CFLAGS="$optarg $QEMU_CFLAGS"
--extra-cflags=*) QEMU_CFLAGS="$QEMU_CFLAGS $optarg"
EXTRA_CFLAGS="$optarg"
;;
--extra-ldflags=*) LDFLAGS="$optarg $LDFLAGS"
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1 change: 0 additions & 1 deletion device_tree.c
Expand Up @@ -18,7 +18,6 @@
#include <unistd.h>
#include <stdlib.h>

#include "config.h"
#include "qemu-common.h"
#include "qemu/error-report.h"
#include "sysemu/device_tree.h"
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2 changes: 1 addition & 1 deletion docs/writing-qmp-commands.txt
Expand Up @@ -598,7 +598,7 @@ stored in its "value" member. In our example, the "value" member is a pointer
to an TimerAlarmMethod instance.

Notice that the "current" variable is used as "true" only in the first
interation of the loop. That's because the alarm timer method in use is the
iteration of the loop. That's because the alarm timer method in use is the
first element of the alarm_timers array. Also notice that QAPI lists are handled
by hand and we return the head of the list.

Expand Down
7 changes: 4 additions & 3 deletions hw/alpha/dp264.c
Expand Up @@ -55,7 +55,7 @@ static void clipper_init(MachineState *machine)
ISABus *isa_bus;
qemu_irq rtc_irq;
long size, i;
const char *palcode_filename;
char *palcode_filename;
uint64_t palcode_entry, palcode_low, palcode_high;
uint64_t kernel_entry, kernel_low, kernel_high;

Expand Down Expand Up @@ -101,8 +101,8 @@ static void clipper_init(MachineState *machine)
/* Load PALcode. Given that this is not "real" cpu palcode,
but one explicitly written for the emulation, we might as
well load it directly from and ELF image. */
palcode_filename = (bios_name ? bios_name : "palcode-clipper");
palcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, palcode_filename);
palcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
bios_name ? bios_name : "palcode-clipper");
if (palcode_filename == NULL) {
hw_error("no palcode provided\n");
exit(1);
Expand All @@ -114,6 +114,7 @@ static void clipper_init(MachineState *machine)
hw_error("could not load palcode '%s'\n", palcode_filename);
exit(1);
}
g_free(palcode_filename);

/* Start all cpus at the PALcode RESET entry point. */
for (i = 0; i < smp_cpus; ++i) {
Expand Down
8 changes: 4 additions & 4 deletions hw/alpha/typhoon.c
Expand Up @@ -841,7 +841,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
}
}

*p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
*p_rtc_irq = qemu_allocate_irq(typhoon_set_timer_irq, s, 0);

/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
but the address space hole reserved at this point is 8TB. */
Expand Down Expand Up @@ -918,11 +918,11 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Init the ISA bus. */
/* ??? Technically there should be a cy82c693ub pci-isa bridge. */
{
qemu_irq isa_pci_irq, *isa_irqs;
qemu_irq *isa_irqs;

*isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io);
isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
isa_irqs = i8259_init(*isa_bus, isa_pci_irq);
isa_irqs = i8259_init(*isa_bus,
qemu_allocate_irq(typhoon_set_isa_irq, s, 0));
isa_bus_irqs(*isa_bus, isa_irqs);
}

Expand Down
5 changes: 2 additions & 3 deletions hw/arm/nseries.c
Expand Up @@ -133,9 +133,8 @@ static void n800_mmc_cs_cb(void *opaque, int line, int level)

static void n8x0_gpio_setup(struct n800_s *s)
{
qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);

qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
}

Expand Down
2 changes: 1 addition & 1 deletion hw/arm/omap_sx1.c
Expand Up @@ -103,7 +103,6 @@ static void sx1_init(MachineState *machine, const int version)
struct omap_mpu_state_s *mpu;
MemoryRegion *address_space = get_system_memory();
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
Expand Down Expand Up @@ -165,6 +164,7 @@ static void sx1_init(MachineState *machine, const int version)

if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size,
&error_abort);
vmstate_register_ram_global(flash_1);
Expand Down
2 changes: 1 addition & 1 deletion hw/display/tc6393xb.c
Expand Up @@ -571,7 +571,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
s->irq = irq;
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);

s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
s->blanked = 1;

s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
Expand Down
1 change: 1 addition & 0 deletions hw/i386/acpi-build.c
Expand Up @@ -596,6 +596,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
}
}
aml_append(parent_scope, method);
qobject_decref(bsel);
}

static void
Expand Down
4 changes: 2 additions & 2 deletions hw/i386/pc.c
Expand Up @@ -1352,9 +1352,9 @@ FWCfgState *pc_memory_init(MachineState *machine,
return fw_cfg;
}

qemu_irq *pc_allocate_cpu_irq(void)
qemu_irq pc_allocate_cpu_irq(void)
{
return qemu_allocate_irqs(pic_irq_request, NULL, 1);
return qemu_allocate_irq(pic_irq_request, NULL, 0);
}

DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
Expand Down
11 changes: 5 additions & 6 deletions hw/i386/pc_piix.c
Expand Up @@ -86,10 +86,9 @@ static void pc_init1(MachineState *machine)
ISABus *isa_bus;
PCII440FXState *i440fx_state;
int piix3_devfn = -1;
qemu_irq *cpu_irq;
qemu_irq *gsi;
qemu_irq *i8259;
qemu_irq *smi_irq;
qemu_irq smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
Expand Down Expand Up @@ -220,13 +219,13 @@ static void pc_init1(MachineState *machine)
} else if (xen_enabled()) {
i8259 = xen_interrupt_controller_init();
} else {
cpu_irq = pc_allocate_cpu_irq();
i8259 = i8259_init(isa_bus, cpu_irq[0]);
i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
}

for (i = 0; i < ISA_NUM_IRQS; i++) {
gsi_state->i8259_irq[i] = i8259[i];
}
g_free(i8259);
if (pci_enabled) {
ioapic_init_gsi(gsi_state, "i440fx");
}
Expand Down Expand Up @@ -284,10 +283,10 @@ static void pc_init1(MachineState *machine)
DeviceState *piix4_pm;
I2CBus *smbus;

smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
gsi[9], *smi_irq,
gsi[9], smi_irq,
kvm_enabled(), fw_cfg, &piix4_pm);
smbus_eeprom_init(smbus, 8, NULL, 0);

Expand Down
4 changes: 1 addition & 3 deletions hw/i386/pc_q35.c
Expand Up @@ -79,7 +79,6 @@ static void pc_q35_init(MachineState *machine)
GSIState *gsi_state;
ISABus *isa_bus;
int pci_enabled = 1;
qemu_irq *cpu_irq;
qemu_irq *gsi;
qemu_irq *i8259;
int i;
Expand Down Expand Up @@ -230,8 +229,7 @@ static void pc_q35_init(MachineState *machine)
} else if (xen_enabled()) {
i8259 = xen_interrupt_controller_init();
} else {
cpu_irq = pc_allocate_cpu_irq();
i8259 = i8259_init(isa_bus, cpu_irq[0]);
i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
}

for (i = 0; i < ISA_NUM_IRQS; i++) {
Expand Down
5 changes: 1 addition & 4 deletions hw/ide/pci.c
Expand Up @@ -452,17 +452,14 @@ static const struct IDEDMAOps bmdma_ops = {

void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
{
qemu_irq *irq;

if (bus->dma == &bm->dma) {
return;
}

bm->dma.ops = &bmdma_ops;
bus->dma = &bm->dma;
bm->irq = bus->irq;
irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
bus->irq = *irq;
bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
bm->pci_dev = d;
}

Expand Down
7 changes: 3 additions & 4 deletions hw/intc/exynos4210_gic.c
Expand Up @@ -213,9 +213,6 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
uint32_t grp, bit, irq_id, n;

for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
s->ext_combiner_irq[n]);

irq_id = 0;
if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
Expand All @@ -230,8 +227,10 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
if (irq_id) {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
s->ext_gic_irq[irq_id-32]);
} else {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
s->ext_combiner_irq[n]);
}

}
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
/* these IDs are passed to Internal Combiner and External GIC */
Expand Down
7 changes: 2 additions & 5 deletions hw/isa/i82378.c
Expand Up @@ -65,7 +65,6 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
uint8_t *pci_conf;
ISABus *isabus;
ISADevice *isa;
qemu_irq *out0_irq;

pci_conf = pci->config;
pci_set_word(pci_conf + PCI_COMMAND,
Expand All @@ -88,11 +87,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
All devices accept byte access only, except timer
*/

/* Workaround the fact that i8259 is not qdev'ified... */
out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);

/* 2 82C59 (irq) */
s->i8259 = i8259_init(isabus, *out0_irq);
s->i8259 = i8259_init(isabus,
qemu_allocate_irq(i82378_request_out0_irq, s, 0));
isa_bus_irqs(isabus, s->i8259);

/* 1 82C54 (pit) */
Expand Down
5 changes: 1 addition & 4 deletions hw/isa/lpc_ich9.c
Expand Up @@ -360,11 +360,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
void ich9_lpc_pm_init(PCIDevice *lpc_pci)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq *sci_irq;

sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1);
ich9_pm_init(lpc_pci, &lpc->pm, sci_irq[0]);

ich9_pm_init(lpc_pci, &lpc->pm, qemu_allocate_irq(ich9_set_sci, lpc, 0));
ich9_lpc_reset(&lpc->d.qdev);
}

Expand Down
10 changes: 4 additions & 6 deletions hw/lm32/lm32_boards.c
Expand Up @@ -78,7 +78,7 @@ static void lm32_evr_init(MachineState *machine)
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
qemu_irq irq[32];
ResetInfo *reset_info;
int i;

Expand Down Expand Up @@ -123,8 +123,7 @@ static void lm32_evr_init(MachineState *machine)
1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
}
Expand Down Expand Up @@ -173,7 +172,7 @@ static void lm32_uclinux_init(MachineState *machine)
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
qemu_irq irq[32];
HWSetup *hw;
ResetInfo *reset_info;
int i;
Expand Down Expand Up @@ -225,8 +224,7 @@ static void lm32_uclinux_init(MachineState *machine)
1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
}
Expand Down
5 changes: 2 additions & 3 deletions hw/lm32/milkymist.c
Expand Up @@ -86,7 +86,7 @@ milkymist_init(MachineState *machine)
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_sdram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
qemu_irq irq[32];
int i;
char *bios_filename;
ResetInfo *reset_info;
Expand Down Expand Up @@ -130,8 +130,7 @@ milkymist_init(MachineState *machine)
2, 0x00, 0x89, 0x00, 0x1d, 1);

/* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
}
Expand Down
2 changes: 1 addition & 1 deletion hw/net/cadence_gem.c
Expand Up @@ -155,7 +155,7 @@
#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */

#define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */
#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
Expand Down
1 change: 1 addition & 0 deletions hw/ppc/e500.c
Expand Up @@ -1030,6 +1030,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
exit(1);
}
}
g_free(filename);

/* Reserve space for dtb */
dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
Expand Down
5 changes: 2 additions & 3 deletions hw/ppc/prep.c
Expand Up @@ -528,7 +528,6 @@ static void ppc_prep_init(MachineState *machine)
PCIDevice *pci;
ISABus *isa_bus;
ISADevice *isa;
qemu_irq *cpu_exit_irq;
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];

Expand Down Expand Up @@ -625,11 +624,11 @@ static void ppc_prep_init(MachineState *machine)

/* PCI -> ISA bridge */
pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
cpu = POWERPC_CPU(first_cpu);
qdev_connect_gpio_out(&pci->qdev, 0,
cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
qdev_connect_gpio_out(&pci->qdev, 1,
qemu_allocate_irq(cpu_request_exit, NULL, 0));
sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
Expand Down

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