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target/riscv: Fix vill field write in vtype
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The guest should be able to set the vill bit as part of vsetvl.

Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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LIU Zhiwei authored and alistair23 committed Feb 10, 2022
1 parent e47c968 commit 29f1c7b
Showing 1 changed file with 1 addition and 0 deletions.
1 change: 1 addition & 0 deletions target/riscv/vector_helper.c
Expand Up @@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
env->vl = vl;
env->vtype = s2;
env->vstart = 0;
env->vill = 0;
return vl;
}

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