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tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
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Implement the new semantics in the fallback expansion.
Change all callers to supply the flags that keep the
semantics unchanged locally.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Jun 29, 2021
1 parent 0b76ff8 commit 2b836c2
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Showing 8 changed files with 100 additions and 55 deletions.
8 changes: 4 additions & 4 deletions include/tcg/tcg-op.h
View file
Expand Up @@ -330,7 +330,7 @@ void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags);
void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
Expand Down Expand Up @@ -528,8 +528,8 @@ void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
Expand Down Expand Up @@ -1192,7 +1192,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
#define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
Expand Down
12 changes: 7 additions & 5 deletions target/arm/translate-a64.c
View file
Expand Up @@ -5437,15 +5437,15 @@ static void handle_rev32(DisasContext *s, unsigned int sf,

/* bswap32_i64 requires zero high word */
tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
tcg_gen_bswap32_i64(tcg_rd, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);

tcg_temp_free_i64(tcg_tmp);
} else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
tcg_gen_bswap32_i64(tcg_rd, tcg_rd, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
}

Expand Down Expand Up @@ -12453,10 +12453,12 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
read_vec_element(s, tcg_tmp, rn, i, grp_size);
switch (grp_size) {
case MO_16:
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp,
TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp,
TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_64:
tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
Expand Down
2 changes: 1 addition & 1 deletion target/arm/translate.c
View file
Expand Up @@ -355,7 +355,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
{
tcg_gen_ext16u_i32(var, var);
tcg_gen_bswap16_i32(var, var);
tcg_gen_bswap16_i32(var, var, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_ext16s_i32(dest, var);
}

Expand Down
2 changes: 1 addition & 1 deletion target/i386/tcg/translate.c
View file
Expand Up @@ -7203,7 +7203,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
{
gen_op_mov_v_reg(s, MO_32, s->T0, reg);
tcg_gen_ext32u_tl(s->T0, s->T0);
tcg_gen_bswap32_tl(s->T0, s->T0);
tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
gen_op_mov_reg_v(s, MO_32, reg, s->T0);
}
break;
Expand Down
2 changes: 1 addition & 1 deletion target/mips/tcg/mxu_translate.c
View file
Expand Up @@ -861,7 +861,7 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)

if (sel == 1) {
/* S32LDDR */
tcg_gen_bswap32_tl(t1, t1);
tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
gen_store_mxu_gpr(t1, XRa);

Expand Down
4 changes: 2 additions & 2 deletions target/s390x/translate.c
View file
Expand Up @@ -3939,13 +3939,13 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)

static DisasJumpType op_rev16(DisasContext *s, DisasOps *o)
{
tcg_gen_bswap16_i64(o->out, o->in2);
tcg_gen_bswap16_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
return DISAS_NEXT;
}

static DisasJumpType op_rev32(DisasContext *s, DisasOps *o)
{
tcg_gen_bswap32_i64(o->out, o->in2);
tcg_gen_bswap32_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
return DISAS_NEXT;
}

Expand Down
2 changes: 1 addition & 1 deletion target/sh4/translate.c
View file
Expand Up @@ -677,7 +677,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv low = tcg_temp_new();
tcg_gen_ext16u_i32(low, REG(B7_4));
tcg_gen_bswap16_i32(low, low);
tcg_gen_bswap16_i32(low, low, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16);
tcg_temp_free(low);
}
Expand Down
123 changes: 83 additions & 40 deletions tcg/tcg-op.c
View file
Expand Up @@ -1001,20 +1001,35 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
}
}

/* Note: we assume the two high bytes are set to zero */
void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
{
/* Only one extension flag may be present. */
tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));

if (TCG_TARGET_HAS_bswap16_i32) {
tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg,
TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg, flags);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();

tcg_gen_shri_i32(t0, arg, 8);
if (!(flags & TCG_BSWAP_IZ)) {
tcg_gen_ext8u_i32(t0, t0);
}

tcg_gen_ext8u_i32(t0, arg);
tcg_gen_shli_i32(t0, t0, 8);
tcg_gen_shri_i32(ret, arg, 8);
tcg_gen_or_i32(ret, ret, t0);
if (flags & TCG_BSWAP_OS) {
tcg_gen_shli_i32(t1, arg, 24);
tcg_gen_sari_i32(t1, t1, 16);
} else if (flags & TCG_BSWAP_OZ) {
tcg_gen_ext8u_i32(t1, arg);
tcg_gen_shli_i32(t1, t1, 8);
} else {
tcg_gen_shli_i32(t1, arg, 8);
}

tcg_gen_or_i32(ret, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
}
}

Expand Down Expand Up @@ -1655,51 +1670,79 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
}
}

/* Note: we assume the six high bytes are set to zero */
void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
{
/* Only one extension flag may be present. */
tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));

if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg), flags);
if (flags & TCG_BSWAP_OS) {
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
} else {
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}
} else if (TCG_TARGET_HAS_bswap16_i64) {
tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg,
TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();

tcg_gen_ext8u_i64(t0, arg);
tcg_gen_shli_i64(t0, t0, 8);
tcg_gen_shri_i64(ret, arg, 8);
tcg_gen_or_i64(ret, ret, t0);
tcg_gen_shri_i64(t0, arg, 8);
if (!(flags & TCG_BSWAP_IZ)) {
tcg_gen_ext8u_i64(t0, t0);
}

if (flags & TCG_BSWAP_OS) {
tcg_gen_shli_i64(t1, arg, 56);
tcg_gen_sari_i64(t1, t1, 48);
} else if (flags & TCG_BSWAP_OZ) {
tcg_gen_ext8u_i64(t1, arg);
tcg_gen_shli_i64(t1, t1, 8);
} else {
tcg_gen_shli_i64(t1, arg, 8);
}

tcg_gen_or_i64(ret, t0, t1);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
}

/* Note: we assume the four high bytes are set to zero */
void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
{
/* Only one extension flag may be present. */
tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));

if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
if (flags & TCG_BSWAP_OS) {
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
} else {
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
}
} else if (TCG_TARGET_HAS_bswap32_i64) {
tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg,
TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff);

/* arg = ....abcd */
tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */
tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */
tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */
tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */
tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */

tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */
tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */
tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */
tcg_gen_or_i64(ret, t0, t1); /* ret = ....dcba */
/* arg = xxxxabcd */
tcg_gen_shri_i64(t0, arg, 8); /* t0 = .xxxxabc */
tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */
tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */
tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */
tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */

tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */
tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */
if (flags & TCG_BSWAP_OS) {
tcg_gen_sari_i64(t1, t1, 32); /* t1 = ssssdc.. */
} else {
tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */
}
tcg_gen_or_i64(ret, t0, t1); /* ret = ssssdcba */

tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
Expand Down Expand Up @@ -2846,7 +2889,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
case MO_16:
tcg_gen_bswap16_i32(val, val);
tcg_gen_bswap16_i32(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext16s_i32(val, val);
}
Expand Down Expand Up @@ -2874,7 +2917,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
switch (memop & MO_SIZE) {
case MO_16:
tcg_gen_ext16u_i32(swap, val);
tcg_gen_bswap16_i32(swap, swap);
tcg_gen_bswap16_i32(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
tcg_gen_bswap32_i32(swap, val);
Expand Down Expand Up @@ -2935,13 +2978,13 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
case MO_16:
tcg_gen_bswap16_i64(val, val);
tcg_gen_bswap16_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext16s_i64(val, val);
}
break;
case MO_32:
tcg_gen_bswap32_i64(val, val);
tcg_gen_bswap32_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext32s_i64(val, val);
}
Expand Down Expand Up @@ -2975,11 +3018,11 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
switch (memop & MO_SIZE) {
case MO_16:
tcg_gen_ext16u_i64(swap, val);
tcg_gen_bswap16_i64(swap, swap);
tcg_gen_bswap16_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
tcg_gen_ext32u_i64(swap, val);
tcg_gen_bswap32_i64(swap, swap);
tcg_gen_bswap32_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_64:
tcg_gen_bswap64_i64(swap, val);
Expand Down

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