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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-201908…
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…29' into staging

ppc patch queue 2018-08-29

Another pull request for ppc-for-4.2.  Includes

  * Several powernv patches which were pulled last minute from the
    last PULL, now that some problems with them have been sorted out
  * A fix for -no-reboot which has been broken since the
    pseries-rhel4.1.0 machine type
  * Add some host threads information which AIX guests will need to
    properly scale the PURR and SPURR
  * Change behaviour to match x86 when unplugging function 0 of a
    multifunction PCI device
  * A number of TCG fixes in FPU emulation

And a handful of other assorted fixes and cleanups.

# gpg: Signature made Thu 29 Aug 2019 06:36:23 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.2-20190829:
  spapr: Set compat mode in spapr_core_plug()
  spapr/pci: Convert types to QEMU coding style
  spapr_pci: Advertise BAR reallocation capability
  spapr: Use SHUTDOWN_CAUSE_SUBSYSTEM_RESET for CAS reboots
  powerpc/spapr: Add host threads parameter to ibm,get_system_parameter
  pseries: Update SLOF firmware image
  target/ppc: Refactor emulation of vmrgew and vmrgow instructions
  target/ppc: Fix do_float_check_status vs inexact
  target/ppc: Set float_tininess_before_rounding at cpu reset
  pseries: Fix compat_pvr on reset
  spapr_pci: remove all child functions in function zero unplug
  ppc: Fix xscvdpspn for SNAN
  ppc: Fix xsmaddmdp and friends
  tests/boot-serial-test: add support for all the PowerNV machines
  ppc/pnv: Introduce PowerNV machines with fixed CPU models
  ppc/pnv: Generate phandle for the "interrupt-parent" property
  ppc/pnv: add more dummy XSCOM addresses for the P9 CAPP
  ppc/pnv: update skiboot to v6.4
  ppc/pnv: Set default ram size to 1.75GB

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@pm215
pm215 committed Sep 3, 2019
2 parents 3483534 + b1e8156 commit 3b3f064
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Showing 22 changed files with 289 additions and 110 deletions.
81 changes: 73 additions & 8 deletions hw/ppc/pnv.c
View file
Expand Up @@ -434,9 +434,14 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
.fdt = fdt,
.offset = isa_offset,
};
uint32_t phandle;

_FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));

phandle = qemu_fdt_alloc_phandle(fdt);
assert(phandle > 0);
_FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));

/* ISA devices are not necessarily parented to the ISA bus so we
* can not use object_child_foreach() */
qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
Expand Down Expand Up @@ -600,9 +605,20 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
pnv_psi_pic_print_info(&chip9->psi, mon);
}

static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
{
PowerPCCPUClass *ppc_default =
POWERPC_CPU_CLASS(object_class_by_name(default_type));
PowerPCCPUClass *ppc =
POWERPC_CPU_CLASS(object_class_by_name(cpu_type));

return ppc_default->pvr_match(ppc_default, ppc->pvr);
}

static void pnv_init(MachineState *machine)
{
PnvMachineState *pnv = PNV_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *ram;
char *fw_filename;
long fw_size;
Expand Down Expand Up @@ -662,13 +678,23 @@ static void pnv_init(MachineState *machine)
}
}

/*
* Check compatibility of the specified CPU with the machine
* default.
*/
if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
error_report("invalid CPU model '%s' for %s machine",
machine->cpu_type, mc->name);
exit(1);
}

/* Create the processor chips */
i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
i, machine->cpu_type);
if (!object_class_by_name(chip_typename)) {
error_report("invalid CPU model '%.*s' for %s machine",
i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
error_report("invalid chip model '%.*s' for %s machine",
i, machine->cpu_type, mc->name);
exit(1);
}

Expand Down Expand Up @@ -1346,25 +1372,47 @@ static void pnv_machine_class_props_init(ObjectClass *oc)
NULL);
}

static void pnv_machine_class_init(ObjectClass *oc, void *data)
static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);

mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");

xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get;
xic->ics_resend = pnv_ics_resend;
}

static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);

mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");

mc->alias = "powernv";
}

static void pnv_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);

mc->desc = "IBM PowerNV (Non-Virtualized)";
mc->init = pnv_init;
mc->reset = pnv_reset;
mc->max_cpus = MAX_CPUS;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
* storage */
mc->no_parallel = 1;
mc->default_boot_order = NULL;
mc->default_ram_size = 1 * GiB;
xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get;
xic->ics_resend = pnv_ics_resend;
/*
* RAM defaults to less than 2048 for 32-bit hosts, and large
* enough to fit the maximum initrd size at it's load address
*/
mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
ispc->print_info = pnv_pic_print_info;

pnv_machine_class_props_init(oc);
Expand All @@ -1384,10 +1432,27 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
.parent = TYPE_PNV9_CHIP, \
}

#define DEFINE_PNV_MACHINE_TYPE(cpu, class_initfn) \
{ \
.name = MACHINE_TYPE_NAME(cpu), \
.parent = TYPE_PNV_MACHINE, \
.instance_size = sizeof(PnvMachineState), \
.instance_init = pnv_machine_instance_init, \
.class_init = class_initfn, \
.interfaces = (InterfaceInfo[]) { \
{ TYPE_XICS_FABRIC }, \
{ TYPE_INTERRUPT_STATS_PROVIDER }, \
{ }, \
}, \
}

static const TypeInfo types[] = {
DEFINE_PNV_MACHINE_TYPE("powernv8", pnv_machine_power8_class_init),
DEFINE_PNV_MACHINE_TYPE("powernv9", pnv_machine_power9_class_init),
{
.name = TYPE_PNV_MACHINE,
.parent = TYPE_MACHINE,
.abstract = true,
.instance_size = sizeof(PnvMachineState),
.instance_init = pnv_machine_instance_init,
.class_init = pnv_machine_class_init,
Expand Down
20 changes: 20 additions & 0 deletions hw/ppc/pnv_xscom.c
View file
Expand Up @@ -106,6 +106,16 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
case 0x201302a: /* CAPP stuff */
case 0x2013801: /* CAPP stuff */
case 0x2013802: /* CAPP stuff */

/* P9 CAPP regs */
case 0x2010841:
case 0x2010842:
case 0x201082a:
case 0x2010828:
case 0x4010841:
case 0x4010842:
case 0x401082a:
case 0x4010828:
return 0;
default:
return -1;
Expand Down Expand Up @@ -138,6 +148,16 @@ static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
case 0x2013801: /* CAPP stuff */
case 0x2013802: /* CAPP stuff */

/* P9 CAPP regs */
case 0x2010841:
case 0x2010842:
case 0x201082a:
case 0x2010828:
case 0x4010841:
case 0x4010842:
case 0x401082a:
case 0x4010828:

/* P8 PRD registers */
case PRD_P8_IPOLL_REG_MASK:
case PRD_P8_IPOLL_REG_STATUS:
Expand Down
29 changes: 26 additions & 3 deletions hw/ppc/spapr.c
View file
Expand Up @@ -1168,6 +1168,7 @@ static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
{
MachineState *machine = MACHINE(spapr);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
int chosen;
const char *boot_device = machine->boot_order;
char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
Expand Down Expand Up @@ -1225,6 +1226,11 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
_FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
}

/* We can deal with BAR reallocation just fine, advertise it to the guest */
if (smc->linux_pci_probe) {
_FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
}

spapr_dt_ov5_platform_support(spapr, fdt, chosen);

g_free(stdout_path);
Expand Down Expand Up @@ -1752,7 +1758,7 @@ static void spapr_machine_reset(MachineState *machine)
spapr_ovec_cleanup(spapr->ov5_cas);
spapr->ov5_cas = spapr_ovec_new();

ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
}

/*
Expand Down Expand Up @@ -3829,6 +3835,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
CPUArchId *core_slot;
int index;
bool hotplugged = spapr_drc_hotplugged(dev);
int i;

core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
if (!core_slot) {
Expand Down Expand Up @@ -3862,13 +3869,26 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
core_slot->cpu = OBJECT(dev);

if (smc->pre_2_10_has_unused_icps) {
int i;

for (i = 0; i < cc->nr_threads; i++) {
cs = CPU(core->threads[i]);
pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
}
}

/*
* Set compatibility mode to match the boot CPU, which was either set
* by the machine reset code or by CAS.
*/
if (hotplugged) {
for (i = 0; i < cc->nr_threads; i++) {
ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
&local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
}
}
}

static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Expand Down Expand Up @@ -4470,6 +4490,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
spapr_caps_add_properties(smc, &error_abort);
smc->irq = &spapr_irq_dual;
smc->dr_phb_enabled = true;
smc->linux_pci_probe = true;
}

static const TypeInfo spapr_machine_info = {
Expand Down Expand Up @@ -4529,12 +4550,14 @@ DEFINE_SPAPR_MACHINE(4_2, "4.2", true);
*/
static void spapr_machine_4_1_class_options(MachineClass *mc)
{
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
static GlobalProperty compat[] = {
/* Only allow 4kiB and 64kiB IOMMU pagesizes */
{ TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
};

spapr_machine_4_2_class_options(mc);
smc->linux_pci_probe = false;
compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
}
Expand Down
5 changes: 0 additions & 5 deletions hw/ppc/spapr_cpu_core.c
View file
Expand Up @@ -41,11 +41,6 @@ static void spapr_cpu_reset(void *opaque)
* using an RTAS call */
cs->halted = 1;

/* Set compatibility mode to match the boot CPU, which was either set
* by the machine reset code or by CAS. This should never fail.
*/
ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);

env->spr[SPR_HIOR] = 0;

lpcr = env->spr[SPR_LPCR];
Expand Down
2 changes: 1 addition & 1 deletion hw/ppc/spapr_hcall.c
View file
Expand Up @@ -1811,7 +1811,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
spapr_ovec_cleanup(ov5_updates);

if (spapr->cas_reboot) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET);
}

return H_SUCCESS;
Expand Down

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