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Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull…
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…-request' into staging

Machine queue + QOM fixes and cleanups

Bug fix:
* numa: hmat: fix cache size check (Igor Mammedov)

QOM fixes and cleanups:
* Move QOM macros and typedefs to header files
* Use TYPE_* constants on TypeInfo structs
* Rename QOM type checking macros for consistency
* Rename enum values and typedefs that conflict with QOM
  type checking amcros
* Fix typos on QOM type checking macros
* Delete unused QOM type checking macros that use
  non-existing typedefs
* hvf: Add missing include
* xen-legacy-backend: Add missing typedef XenLegacyDevice

# gpg: Signature made Thu 27 Aug 2020 20:20:05 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (53 commits)
  dc390: Use TYPE_DC390_DEVICE constant
  ppce500: Use TYPE_PPC_E500_PCI_BRIDGE constant
  tosa: Use TYPE_TOSA_MISC_GPIO constant
  xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant
  sclpconsole: Use TYPE_* constants
  amd_iommu: Use TYPE_AMD_IOMMU_PCI constant
  nios2_iic: Use TYPE_ALTERA_IIC constant
  etsec: Use TYPE_ETSEC_COMMON constant
  migration: Rename class type checking macros
  swim: Rename struct SWIM to Swim
  s390-virtio-ccw: Rename S390_MACHINE_CLASS macro
  nubus: Rename class type checking macros
  vfio/pci: Move QOM macros to header
  kvm: Move QOM macros to kvm.h
  mptsas: Move QOM macros to header
  pxa2xx: Move QOM macros to header
  rocker: Move QOM macros to header
  auxbus: Move QOM macros to header
  piix: Move QOM macros to header
  virtio-serial-bus: Move QOM macros to header
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@pm215
pm215 committed Aug 28, 2020
2 parents 3326572 + 9295131 commit 3e39dac
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Showing 90 changed files with 621 additions and 621 deletions.
4 changes: 2 additions & 2 deletions block/throttle-groups.c
View file
Expand Up @@ -63,7 +63,7 @@ static void timer_cb(ThrottleGroupMember *tgm, bool is_write);
* access some other ThrottleGroupMember's timers only after verifying that
* that ThrottleGroupMember has throttled requests in the queue.
*/
typedef struct ThrottleGroup {
struct ThrottleGroup {
Object parent_obj;

/* refuse individual property change if initialization is complete */
Expand All @@ -79,7 +79,7 @@ typedef struct ThrottleGroup {

/* This field is protected by the global QEMU mutex */
QTAILQ_ENTRY(ThrottleGroup) list;
} ThrottleGroup;
};

/* This is protected by the global QEMU mutex */
static QTAILQ_HEAD(, ThrottleGroup) throttle_groups =
Expand Down
124 changes: 62 additions & 62 deletions hw/arm/allwinner-h3.c
View file
Expand Up @@ -35,37 +35,37 @@

/* Memory map */
const hwaddr allwinner_h3_memmap[] = {
[AW_H3_SRAM_A1] = 0x00000000,
[AW_H3_SRAM_A2] = 0x00044000,
[AW_H3_SRAM_C] = 0x00010000,
[AW_H3_SYSCTRL] = 0x01c00000,
[AW_H3_MMC0] = 0x01c0f000,
[AW_H3_SID] = 0x01c14000,
[AW_H3_EHCI0] = 0x01c1a000,
[AW_H3_OHCI0] = 0x01c1a400,
[AW_H3_EHCI1] = 0x01c1b000,
[AW_H3_OHCI1] = 0x01c1b400,
[AW_H3_EHCI2] = 0x01c1c000,
[AW_H3_OHCI2] = 0x01c1c400,
[AW_H3_EHCI3] = 0x01c1d000,
[AW_H3_OHCI3] = 0x01c1d400,
[AW_H3_CCU] = 0x01c20000,
[AW_H3_PIT] = 0x01c20c00,
[AW_H3_UART0] = 0x01c28000,
[AW_H3_UART1] = 0x01c28400,
[AW_H3_UART2] = 0x01c28800,
[AW_H3_UART3] = 0x01c28c00,
[AW_H3_EMAC] = 0x01c30000,
[AW_H3_DRAMCOM] = 0x01c62000,
[AW_H3_DRAMCTL] = 0x01c63000,
[AW_H3_DRAMPHY] = 0x01c65000,
[AW_H3_GIC_DIST] = 0x01c81000,
[AW_H3_GIC_CPU] = 0x01c82000,
[AW_H3_GIC_HYP] = 0x01c84000,
[AW_H3_GIC_VCPU] = 0x01c86000,
[AW_H3_RTC] = 0x01f00000,
[AW_H3_CPUCFG] = 0x01f01c00,
[AW_H3_SDRAM] = 0x40000000
[AW_H3_DEV_SRAM_A1] = 0x00000000,
[AW_H3_DEV_SRAM_A2] = 0x00044000,
[AW_H3_DEV_SRAM_C] = 0x00010000,
[AW_H3_DEV_SYSCTRL] = 0x01c00000,
[AW_H3_DEV_MMC0] = 0x01c0f000,
[AW_H3_DEV_SID] = 0x01c14000,
[AW_H3_DEV_EHCI0] = 0x01c1a000,
[AW_H3_DEV_OHCI0] = 0x01c1a400,
[AW_H3_DEV_EHCI1] = 0x01c1b000,
[AW_H3_DEV_OHCI1] = 0x01c1b400,
[AW_H3_DEV_EHCI2] = 0x01c1c000,
[AW_H3_DEV_OHCI2] = 0x01c1c400,
[AW_H3_DEV_EHCI3] = 0x01c1d000,
[AW_H3_DEV_OHCI3] = 0x01c1d400,
[AW_H3_DEV_CCU] = 0x01c20000,
[AW_H3_DEV_PIT] = 0x01c20c00,
[AW_H3_DEV_UART0] = 0x01c28000,
[AW_H3_DEV_UART1] = 0x01c28400,
[AW_H3_DEV_UART2] = 0x01c28800,
[AW_H3_DEV_UART3] = 0x01c28c00,
[AW_H3_DEV_EMAC] = 0x01c30000,
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
[AW_H3_DEV_DRAMPHY] = 0x01c65000,
[AW_H3_DEV_GIC_DIST] = 0x01c81000,
[AW_H3_DEV_GIC_CPU] = 0x01c82000,
[AW_H3_DEV_GIC_HYP] = 0x01c84000,
[AW_H3_DEV_GIC_VCPU] = 0x01c86000,
[AW_H3_DEV_RTC] = 0x01f00000,
[AW_H3_DEV_CPUCFG] = 0x01f01c00,
[AW_H3_DEV_SDRAM] = 0x40000000
};

/* List of unimplemented devices */
Expand Down Expand Up @@ -183,7 +183,7 @@ void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
}

rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
rom_size, s->memmap[AW_H3_SRAM_A1],
rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
NULL, NULL, NULL, NULL, false);
}

Expand Down Expand Up @@ -262,10 +262,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);

sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);

/*
* Wire the outputs from each CPU's generic timer and the GICv3
Expand Down Expand Up @@ -312,7 +312,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)

/* Timer */
sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
Expand All @@ -325,32 +325,32 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
32 * KiB, &error_abort);
memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
44 * KiB, &error_abort);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
&s->sram_a1);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
&s->sram_a2);
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
&s->sram_c);

/* Clock Control Unit */
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);

/* System Control */
sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);

/* CPU Configuration */
sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);

/* Security Identifier */
sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);

/* SD/MMC */
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));

Expand All @@ -364,63 +364,63 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));

/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI0));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI1));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI2));
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_EHCI3));

sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI0));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI1));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI2));
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
qdev_get_gpio_in(DEVICE(&s->gic),
AW_H3_GIC_SPI_OHCI3));

/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
/* UART1 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
/* UART2 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
/* UART3 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);

/* DRAMC */
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);

/* RTC */
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);

/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
Expand Down
24 changes: 12 additions & 12 deletions hw/arm/armsse.c
View file
Expand Up @@ -167,7 +167,7 @@ static void irq_status_forwarder(void *opaque, int n, int level)

static void nsccfg_handler(void *opaque, int n, int level)
{
ARMSSE *s = ARMSSE(opaque);
ARMSSE *s = ARM_SSE(opaque);

s->nsccfg = level;
}
Expand Down Expand Up @@ -233,8 +233,8 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)

static void armsse_init(Object *obj)
{
ARMSSE *s = ARMSSE(obj);
ARMSSEClass *asc = ARMSSE_GET_CLASS(obj);
ARMSSE *s = ARM_SSE(obj);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(obj);
const ARMSSEInfo *info = asc->info;
int i;

Expand Down Expand Up @@ -391,7 +391,7 @@ static void armsse_exp_irq(void *opaque, int n, int level)

static void armsse_mpcexp_status(void *opaque, int n, int level)
{
ARMSSE *s = ARMSSE(opaque);
ARMSSE *s = ARM_SSE(opaque);
qemu_set_irq(s->mpcexp_status_in[n], level);
}

Expand All @@ -401,7 +401,7 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno)
* Return a qemu_irq which can be used to signal IRQ n to
* all CPUs in the SSE.
*/
ARMSSEClass *asc = ARMSSE_GET_CLASS(s);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(s);
const ARMSSEInfo *info = asc->info;

assert(irq_is_common[irqno]);
Expand All @@ -428,8 +428,8 @@ static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr)

static void armsse_realize(DeviceState *dev, Error **errp)
{
ARMSSE *s = ARMSSE(dev);
ARMSSEClass *asc = ARMSSE_GET_CLASS(dev);
ARMSSE *s = ARM_SSE(dev);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
const ARMSSEInfo *info = asc->info;
int i;
MemoryRegion *mr;
Expand Down Expand Up @@ -1114,7 +1114,7 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
* of the address bits. The NSC attribute is guest-adjustable via the
* NSCCFG register in the security controller.
*/
ARMSSE *s = ARMSSE(ii);
ARMSSE *s = ARM_SSE(ii);
int region = extract32(address, 28, 4);

*ns = !(region & 1);
Expand All @@ -1136,7 +1136,7 @@ static const VMStateDescription armsse_vmstate = {

static void armsse_reset(DeviceState *dev)
{
ARMSSE *s = ARMSSE(dev);
ARMSSE *s = ARM_SSE(dev);

s->nsccfg = 0;
}
Expand All @@ -1145,7 +1145,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass);
ARMSSEClass *asc = ARMSSE_CLASS(klass);
ARMSSEClass *asc = ARM_SSE_CLASS(klass);
const ARMSSEInfo *info = data;

dc->realize = armsse_realize;
Expand All @@ -1157,7 +1157,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
}

static const TypeInfo armsse_info = {
.name = TYPE_ARMSSE,
.name = TYPE_ARM_SSE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMSSE),
.instance_init = armsse_init,
Expand All @@ -1177,7 +1177,7 @@ static void armsse_register_types(void)
for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) {
TypeInfo ti = {
.name = armsse_variants[i].name,
.parent = TYPE_ARMSSE,
.parent = TYPE_ARM_SSE,
.class_init = armsse_class_init,
.class_data = (void *)&armsse_variants[i],
};
Expand Down
4 changes: 2 additions & 2 deletions hw/arm/aspeed.c
View file
Expand Up @@ -309,7 +309,7 @@ static void aspeed_machine_init(MachineState *machine)
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);

memory_region_add_subregion(get_system_memory(),
sc->memmap[ASPEED_SDRAM],
sc->memmap[ASPEED_DEV_SDRAM],
&bmc->ram_container);

max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
Expand Down Expand Up @@ -360,7 +360,7 @@ static void aspeed_machine_init(MachineState *machine)
}

aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
aspeed_board_binfo.nb_cpus = sc->num_cpus;

if (amc->i2c_init) {
Expand Down

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