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target/loongarch: Implement xvsrln xvsran
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This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-39-gaosong@loongson.cn>
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gaosong-loongson committed Sep 20, 2023
1 parent 8c272fe commit 40c7674
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Showing 4 changed files with 137 additions and 75 deletions.
16 changes: 16 additions & 0 deletions target/loongarch/disas.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2104,6 +2104,22 @@ INSN_LASX(xvsrari_h, vv_i)
INSN_LASX(xvsrari_w, vv_i)
INSN_LASX(xvsrari_d, vv_i)

INSN_LASX(xvsrln_b_h, vvv)
INSN_LASX(xvsrln_h_w, vvv)
INSN_LASX(xvsrln_w_d, vvv)
INSN_LASX(xvsran_b_h, vvv)
INSN_LASX(xvsran_h_w, vvv)
INSN_LASX(xvsran_w_d, vvv)

INSN_LASX(xvsrlni_b_h, vv_i)
INSN_LASX(xvsrlni_h_w, vv_i)
INSN_LASX(xvsrlni_w_d, vv_i)
INSN_LASX(xvsrlni_d_q, vv_i)
INSN_LASX(xvsrani_b_h, vv_i)
INSN_LASX(xvsrani_h_w, vv_i)
INSN_LASX(xvsrani_w_d, vv_i)
INSN_LASX(xvsrani_d_q, vv_i)

INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
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14 changes: 14 additions & 0 deletions target/loongarch/insn_trans/trans_vec.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -3771,6 +3771,12 @@ TRANS(vsrln_w_d, LSX, gen_vvv, gen_helper_vsrln_w_d)
TRANS(vsran_b_h, LSX, gen_vvv, gen_helper_vsran_b_h)
TRANS(vsran_h_w, LSX, gen_vvv, gen_helper_vsran_h_w)
TRANS(vsran_w_d, LSX, gen_vvv, gen_helper_vsran_w_d)
TRANS(xvsrln_b_h, LASX, gen_xxx, gen_helper_vsrln_b_h)
TRANS(xvsrln_h_w, LASX, gen_xxx, gen_helper_vsrln_h_w)
TRANS(xvsrln_w_d, LASX, gen_xxx, gen_helper_vsrln_w_d)
TRANS(xvsran_b_h, LASX, gen_xxx, gen_helper_vsran_b_h)
TRANS(xvsran_h_w, LASX, gen_xxx, gen_helper_vsran_h_w)
TRANS(xvsran_w_d, LASX, gen_xxx, gen_helper_vsran_w_d)

TRANS(vsrlni_b_h, LSX, gen_vv_i, gen_helper_vsrlni_b_h)
TRANS(vsrlni_h_w, LSX, gen_vv_i, gen_helper_vsrlni_h_w)
Expand All @@ -3780,6 +3786,14 @@ TRANS(vsrani_b_h, LSX, gen_vv_i, gen_helper_vsrani_b_h)
TRANS(vsrani_h_w, LSX, gen_vv_i, gen_helper_vsrani_h_w)
TRANS(vsrani_w_d, LSX, gen_vv_i, gen_helper_vsrani_w_d)
TRANS(vsrani_d_q, LSX, gen_vv_i, gen_helper_vsrani_d_q)
TRANS(xvsrlni_b_h, LASX, gen_xx_i, gen_helper_vsrlni_b_h)
TRANS(xvsrlni_h_w, LASX, gen_xx_i, gen_helper_vsrlni_h_w)
TRANS(xvsrlni_w_d, LASX, gen_xx_i, gen_helper_vsrlni_w_d)
TRANS(xvsrlni_d_q, LASX, gen_xx_i, gen_helper_vsrlni_d_q)
TRANS(xvsrani_b_h, LASX, gen_xx_i, gen_helper_vsrani_b_h)
TRANS(xvsrani_h_w, LASX, gen_xx_i, gen_helper_vsrani_h_w)
TRANS(xvsrani_w_d, LASX, gen_xx_i, gen_helper_vsrani_w_d)
TRANS(xvsrani_d_q, LASX, gen_xx_i, gen_helper_vsrani_d_q)

TRANS(vsrlrn_b_h, LSX, gen_vvv, gen_helper_vsrlrn_b_h)
TRANS(vsrlrn_h_w, LSX, gen_vvv, gen_helper_vsrlrn_h_w)
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16 changes: 16 additions & 0 deletions target/loongarch/insns.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -1678,6 +1678,22 @@ xvsrari_h 0111 01101010 10000 1 .... ..... ..... @vv_ui4
xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5
xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6

xvsrln_b_h 0111 01001111 01001 ..... ..... ..... @vvv
xvsrln_h_w 0111 01001111 01010 ..... ..... ..... @vvv
xvsrln_w_d 0111 01001111 01011 ..... ..... ..... @vvv
xvsran_b_h 0111 01001111 01101 ..... ..... ..... @vvv
xvsran_h_w 0111 01001111 01110 ..... ..... ..... @vvv
xvsran_w_d 0111 01001111 01111 ..... ..... ..... @vvv

xvsrlni_b_h 0111 01110100 00000 1 .... ..... ..... @vv_ui4
xvsrlni_h_w 0111 01110100 00001 ..... ..... ..... @vv_ui5
xvsrlni_w_d 0111 01110100 0001 ...... ..... ..... @vv_ui6
xvsrlni_d_q 0111 01110100 001 ....... ..... ..... @vv_ui7
xvsrani_b_h 0111 01110101 10000 1 .... ..... ..... @vv_ui4
xvsrani_h_w 0111 01110101 10001 ..... ..... ..... @vv_ui5
xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6
xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7

xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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166 changes: 91 additions & 75 deletions target/loongarch/vec_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1109,105 +1109,121 @@ VSRARI(vsrari_d, 64, D)

#define R_SHIFT(a, b) (a >> b)

#define VSRLN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = R_SHIFT((T)Vj->E2(i),((T)Vk->E2(i)) % BIT); \
} \
Vd->D(1) = 0; \
#define VSRLN(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i, j, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
Vd->E1(j + ofs * 2 * i) = R_SHIFT(Vj->E2(j + ofs * i), \
Vk->E2(j + ofs * i) % BIT); \
} \
Vd->D(2 * i + 1) = 0; \
} \
}

VSRLN(vsrln_b_h, 16, uint16_t, B, H)
VSRLN(vsrln_h_w, 32, uint32_t, H, W)
VSRLN(vsrln_w_d, 64, uint64_t, W, D)
VSRLN(vsrln_b_h, 16, B, UH)
VSRLN(vsrln_h_w, 32, H, UW)
VSRLN(vsrln_w_d, 64, W, UD)

#define VSRAN(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
\
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E1(i) = R_SHIFT(Vj->E2(i), ((T)Vk->E2(i)) % BIT); \
} \
Vd->D(1) = 0; \
#define VSRAN(NAME, BIT, E1, E2, E3) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i, j, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
Vd->E1(j + ofs * 2 * i) = R_SHIFT(Vj->E2(j + ofs * i), \
Vk->E3(j + ofs * i) % BIT); \
} \
Vd->D(2 * i + 1) = 0; \
} \
}

VSRAN(vsran_b_h, 16, uint16_t, B, H)
VSRAN(vsran_h_w, 32, uint32_t, H, W)
VSRAN(vsran_w_d, 64, uint64_t, W, D)
VSRAN(vsran_b_h, 16, B, H, UH)
VSRAN(vsran_h_w, 32, H, W, UW)
VSRAN(vsran_w_d, 64, W, D, UD)

#define VSRLNI(NAME, BIT, T, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = R_SHIFT((T)Vj->E2(i), imm); \
temp.E1(i + max) = R_SHIFT((T)Vd->E2(i), imm); \
} \
*Vd = temp; \
#define VSRLNI(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i, j, ofs; \
VReg temp = {}; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
temp.E1(j + ofs * 2 * i) = R_SHIFT(Vj->E2(j + ofs * i), imm); \
temp.E1(j + ofs * (2 * i + 1)) = R_SHIFT(Vd->E2(j + ofs * i), \
imm); \
} \
} \
*Vd = temp; \
}

void HELPER(vsrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
VReg temp;
int i;
VReg temp = {};
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;

temp.D(0) = 0;
temp.D(1) = 0;
temp.D(0) = int128_getlo(int128_urshift(Vj->Q(0), imm % 128));
temp.D(1) = int128_getlo(int128_urshift(Vd->Q(0), imm % 128));
for (i = 0; i < 2; i++) {
temp.D(2 * i) = int128_getlo(int128_urshift(Vj->Q(i), imm % 128));
temp.D(2 * i +1) = int128_getlo(int128_urshift(Vd->Q(i), imm % 128));
}
*Vd = temp;
}

VSRLNI(vsrlni_b_h, 16, uint16_t, B, H)
VSRLNI(vsrlni_h_w, 32, uint32_t, H, W)
VSRLNI(vsrlni_w_d, 64, uint64_t, W, D)
VSRLNI(vsrlni_b_h, 16, B, UH)
VSRLNI(vsrlni_h_w, 32, H, UW)
VSRLNI(vsrlni_w_d, 64, W, UD)

#define VSRANI(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i, max; \
VReg temp; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
\
temp.D(0) = 0; \
temp.D(1) = 0; \
max = LSX_LEN/BIT; \
for (i = 0; i < max; i++) { \
temp.E1(i) = R_SHIFT(Vj->E2(i), imm); \
temp.E1(i + max) = R_SHIFT(Vd->E2(i), imm); \
} \
*Vd = temp; \
#define VSRANI(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i, j, ofs; \
VReg temp = {}; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
temp.E1(j + ofs * 2 * i) = R_SHIFT(Vj->E2(j + ofs * i), imm); \
temp.E1(j + ofs * (2 * i + 1)) = R_SHIFT(Vd->E2(j + ofs * i), \
imm); \
} \
} \
*Vd = temp; \
}

void HELPER(vsrani_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
VReg temp;
int i;
VReg temp = {};
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;

temp.D(0) = 0;
temp.D(1) = 0;
temp.D(0) = int128_getlo(int128_rshift(Vj->Q(0), imm % 128));
temp.D(1) = int128_getlo(int128_rshift(Vd->Q(0), imm % 128));
for (i = 0; i < 2; i++) {
temp.D(2 * i) = int128_getlo(int128_rshift(Vj->Q(i), imm % 128));
temp.D(2 * i + 1) = int128_getlo(int128_rshift(Vd->Q(i), imm % 128));
}
*Vd = temp;
}

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