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Merge tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu …
…into staging * Fix s390x CPU reconfiguration information in the SCLP facility map * Fix condition code problem in the CLC and LAALG instruction * Fix ordering of the new s390x topology list entries * Add some more files to the MAINTAINERS file * Allow newer versions of Tesseract in the m68k nextcube test # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVKgksRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWIHg//TM3JOpsMEqHKlUKqOJH02mFQrK6H7LG0 # BC56FG7T+/mpYs1NTG92t8nCK03C2ZCweQWD7ZulRJAjPhZv+TF5bJEForivU7+k # PKEshz9xKCWn2YGyNnf2LA06J1JkF215+KlReOoxwSgj1cPlHfBLQ0DtxmpJJZ1G # h5p4d26BbSlwR58HrFWTlhgJMPenl59BETUGIK1FklBxunmZeeijddfniAhOT44y # i0u9/H9KCg3tkwBROUy+42QV+ef32kz/yvi5RmYQI5W7PixO4sxH6MYduOjshsu9 # wK70f8EOwiZV6lFxqmbV7vxFeNnp5IuaVU7PMBoAkwZqLw99mSFy1+1BabCuL5b+ # 3iUTiD4UW48MYwE2Ua6Lit4kpfjhwcp/UYz6pIk6TCBQX6LfzO+nj+rod0GdIpyZ # 4Lwm7jBtpTlYkGrsMvpA/qcidOtqPA1lmBTNlY1hFodQF6KWtyObn0w5AM80xeeU # /mGxQDz97Bpz7LKZvhu+k38jaWvnJFnl3jF1zet88CYL9YL+YI/k1KjhFafCXb0V # 38Xpt5JTWxyLSh2B3gx0OpokX5bftvW9GlLix0HqL7c23uYwR2Bq+Rd6I8SAlk4C # uJq6gqP8IFBFHfgbmyqf/fyd/eHxm7J1voIdy9PZyxZ1JYT9A7yu56qV6SJYwCpr # aARwui/Dm4o= # =y+cC # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 02:30:35 HKT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu: target/s390x/cpu topology: Fix ordering and creation of TLEs tests/tcg/s390x: Test ADD LOGICAL WITH CARRY tests/tcg/s390x: Test LAALG with negative cc_src target/s390x: Fix LAALG not updating cc_src tests/tcg/s390x: Test CLC with inaccessible second operand target/s390x: Fix CLC corrupting cc_src target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block() s390/sclp: fix SCLP facility map tests/avocado: Allow newer versions of tesseract in the nextcube test MAINTAINERS: Add artist.c to the hppa machine section MAINTAINERS: Add the virtio-gpu documentation to the corresponding section Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,156 @@ | ||
| /* | ||
| * Test ADD LOGICAL WITH CARRY instructions. | ||
| * | ||
| * SPDX-License-Identifier: GPL-2.0-or-later | ||
| */ | ||
| #include <stdio.h> | ||
| #include <stdlib.h> | ||
|
|
||
| static const struct test { | ||
| const char *name; | ||
| unsigned long values[3]; | ||
| unsigned long exp_sum; | ||
| int exp_cc; | ||
| } tests[] = { | ||
| /* | ||
| * Each test starts with CC 0 and executes two chained ADD LOGICAL WITH | ||
| * CARRY instructions on three input values. The values must be compatible | ||
| * with both 32- and 64-bit test functions. | ||
| */ | ||
|
|
||
| /* NAME VALUES EXP_SUM EXP_CC */ | ||
| { "cc0->cc0", {0, 0, 0}, 0, 0, }, | ||
| { "cc0->cc1", {0, 0, 42}, 42, 1, }, | ||
| /* cc0->cc2 is not possible */ | ||
| /* cc0->cc3 is not possible */ | ||
| /* cc1->cc0 is not possible */ | ||
| { "cc1->cc1", {-3, 1, 1}, -1, 1, }, | ||
| { "cc1->cc2", {-3, 1, 2}, 0, 2, }, | ||
| { "cc1->cc3", {-3, 1, -1}, -3, 3, }, | ||
| /* cc2->cc0 is not possible */ | ||
| { "cc2->cc1", {-1, 1, 1}, 2, 1, }, | ||
| { "cc2->cc2", {-1, 1, -1}, 0, 2, }, | ||
| /* cc2->cc3 is not possible */ | ||
| /* cc3->cc0 is not possible */ | ||
| { "cc3->cc1", {-1, 2, 1}, 3, 1, }, | ||
| { "cc3->cc2", {-1, 2, -2}, 0, 2, }, | ||
| { "cc3->cc3", {-1, 2, -1}, 1, 3, }, | ||
| }; | ||
|
|
||
| /* Test ALCR (register variant) followed by ALC (memory variant). */ | ||
| static unsigned long test32rm(unsigned long a, unsigned long b, | ||
| unsigned long c, int *cc) | ||
| { | ||
| unsigned int a32 = a, b32 = b, c32 = c; | ||
|
|
||
| asm("xr %[cc],%[cc]\n" | ||
| "alcr %[a],%[b]\n" | ||
| "alc %[a],%[c]\n" | ||
| "ipm %[cc]" | ||
| : [a] "+&r" (a32), [cc] "+&r" (*cc) | ||
| : [b] "r" (b32), [c] "T" (c32) | ||
| : "cc"); | ||
| *cc >>= 28; | ||
|
|
||
| return (int)a32; | ||
| } | ||
|
|
||
| /* Test ALC (memory variant) followed by ALCR (register variant). */ | ||
| static unsigned long test32mr(unsigned long a, unsigned long b, | ||
| unsigned long c, int *cc) | ||
| { | ||
| unsigned int a32 = a, b32 = b, c32 = c; | ||
|
|
||
| asm("xr %[cc],%[cc]\n" | ||
| "alc %[a],%[b]\n" | ||
| "alcr %[c],%[a]\n" | ||
| "ipm %[cc]" | ||
| : [a] "+&r" (a32), [c] "+&r" (c32), [cc] "+&r" (*cc) | ||
| : [b] "T" (b32) | ||
| : "cc"); | ||
| *cc >>= 28; | ||
|
|
||
| return (int)c32; | ||
| } | ||
|
|
||
| /* Test ALCGR (register variant) followed by ALCG (memory variant). */ | ||
| static unsigned long test64rm(unsigned long a, unsigned long b, | ||
| unsigned long c, int *cc) | ||
| { | ||
| asm("xr %[cc],%[cc]\n" | ||
| "alcgr %[a],%[b]\n" | ||
| "alcg %[a],%[c]\n" | ||
| "ipm %[cc]" | ||
| : [a] "+&r" (a), [cc] "+&r" (*cc) | ||
| : [b] "r" (b), [c] "T" (c) | ||
| : "cc"); | ||
| *cc >>= 28; | ||
| return a; | ||
| } | ||
|
|
||
| /* Test ALCG (memory variant) followed by ALCGR (register variant). */ | ||
| static unsigned long test64mr(unsigned long a, unsigned long b, | ||
| unsigned long c, int *cc) | ||
| { | ||
| asm("xr %[cc],%[cc]\n" | ||
| "alcg %[a],%[b]\n" | ||
| "alcgr %[c],%[a]\n" | ||
| "ipm %[cc]" | ||
| : [a] "+&r" (a), [c] "+&r" (c), [cc] "+&r" (*cc) | ||
| : [b] "T" (b) | ||
| : "cc"); | ||
| *cc >>= 28; | ||
| return c; | ||
| } | ||
|
|
||
| static const struct test_func { | ||
| const char *name; | ||
| unsigned long (*ptr)(unsigned long, unsigned long, unsigned long, int *); | ||
| } test_funcs[] = { | ||
| { "test32rm", test32rm }, | ||
| { "test32mr", test32mr }, | ||
| { "test64rm", test64rm }, | ||
| { "test64mr", test64mr }, | ||
| }; | ||
|
|
||
| static const struct test_perm { | ||
| const char *name; | ||
| size_t a_idx, b_idx, c_idx; | ||
| } test_perms[] = { | ||
| { "a, b, c", 0, 1, 2 }, | ||
| { "b, a, c", 1, 0, 2 }, | ||
| }; | ||
|
|
||
| int main(void) | ||
| { | ||
| unsigned long a, b, c, sum; | ||
| int result = EXIT_SUCCESS; | ||
| const struct test_func *f; | ||
| const struct test_perm *p; | ||
| size_t i, j, k; | ||
| const struct test *t; | ||
| int cc; | ||
|
|
||
| for (i = 0; i < sizeof(tests) / sizeof(tests[0]); i++) { | ||
| t = &tests[i]; | ||
| for (j = 0; j < sizeof(test_funcs) / sizeof(test_funcs[0]); j++) { | ||
| f = &test_funcs[j]; | ||
| for (k = 0; k < sizeof(test_perms) / sizeof(test_perms[0]); k++) { | ||
| p = &test_perms[k]; | ||
| a = t->values[p->a_idx]; | ||
| b = t->values[p->b_idx]; | ||
| c = t->values[p->c_idx]; | ||
| sum = f->ptr(a, b, c, &cc); | ||
| if (sum != t->exp_sum || cc != t->exp_cc) { | ||
| fprintf(stderr, | ||
| "[ FAILED ] %s %s(0x%lx, 0x%lx, 0x%lx) returned 0x%lx cc %d, expected 0x%lx cc %d\n", | ||
| t->name, f->name, a, b, c, sum, cc, | ||
| t->exp_sum, t->exp_cc); | ||
| result = EXIT_FAILURE; | ||
| } | ||
| } | ||
| } | ||
| } | ||
|
|
||
| return result; | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,48 @@ | ||
| /* | ||
| * Test the CLC instruction. | ||
| * | ||
| * SPDX-License-Identifier: GPL-2.0-or-later | ||
| */ | ||
| #include <assert.h> | ||
| #include <signal.h> | ||
| #include <stdlib.h> | ||
| #include <string.h> | ||
| #include <unistd.h> | ||
|
|
||
| static void handle_sigsegv(int sig, siginfo_t *info, void *ucontext) | ||
| { | ||
| mcontext_t *mcontext = &((ucontext_t *)ucontext)->uc_mcontext; | ||
| if (mcontext->gregs[0] != 600) { | ||
| write(STDERR_FILENO, "bad r0\n", 7); | ||
| _exit(EXIT_FAILURE); | ||
| } | ||
| if (((mcontext->psw.mask >> 44) & 3) != 1) { | ||
| write(STDERR_FILENO, "bad cc\n", 7); | ||
| _exit(EXIT_FAILURE); | ||
| } | ||
| _exit(EXIT_SUCCESS); | ||
| } | ||
|
|
||
| int main(void) | ||
| { | ||
| register unsigned long r0 asm("r0"); | ||
| unsigned long mem = 42, rhs = 500; | ||
| struct sigaction act; | ||
| int err; | ||
|
|
||
| memset(&act, 0, sizeof(act)); | ||
| act.sa_sigaction = handle_sigsegv; | ||
| act.sa_flags = SA_SIGINFO; | ||
| err = sigaction(SIGSEGV, &act, NULL); | ||
| assert(err == 0); | ||
|
|
||
| r0 = 100; | ||
| asm("algr %[r0],%[rhs]\n" | ||
| "clc 0(8,%[mem]),0(0)\n" /* The 2nd operand will cause a SEGV. */ | ||
| : [r0] "+r" (r0) | ||
| : [mem] "r" (&mem) | ||
| , [rhs] "r" (rhs) | ||
| : "cc", "memory"); | ||
|
|
||
| return EXIT_FAILURE; | ||
| } |
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