tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero

Fixes: 92c041c ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
qemu · Oct 18, 2023 · 451ae08 · 451ae08
1 parent 0396dd7
commit 451ae08
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
@@ -2076,8 +2076,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
     }
 
 #if !defined(CONFIG_SOFTMMU)
-    tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
-    tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+    if (guest_base) {
+        tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+        tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+    }
 #endif
 
     /* Call generated code */