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target/arm: Implement SVE2 SHRN, RSHRN
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@rth7680 @pm215
rth7680 authored and pm215 committed May 25, 2021
1 parent b87dbee commit 46d111b
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Showing 4 changed files with 236 additions and 2 deletions.
16 changes: 16 additions & 0 deletions target/arm/helper-sve.h
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Expand Up @@ -2444,6 +2444,22 @@ DEF_HELPER_FLAGS_3(sve2_sqxtunt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sqxtunt_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sqxtunt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(sve2_shrnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_shrnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_shrnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(sve2_shrnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_shrnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_shrnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(sve2_rshrnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_rshrnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_rshrnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_3(sve2_rshrnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_rshrnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_rshrnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
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8 changes: 8 additions & 0 deletions target/arm/sve.decode
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Expand Up @@ -1285,6 +1285,14 @@ UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl
SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl
SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl

## SVE2 bitwise shift right narrow

# Bit 23 == 0 is handled by esz > 0 in the translator.
SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr
SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr
RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr
RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr

## SVE2 floating-point pairwise operations

FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
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54 changes: 52 additions & 2 deletions target/arm/sve_helper.c
View file
Expand Up @@ -1868,6 +1868,17 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \
when N is negative, add 2**M-1. */
#define DO_ASRD(N, M) ((N + (N < 0 ? ((__typeof(N))1 << M) - 1 : 0)) >> M)

static inline uint64_t do_urshr(uint64_t x, unsigned sh)
{
if (likely(sh < 64)) {
return (x >> sh) + ((x >> (sh - 1)) & 1);
} else if (sh == 64) {
return x >> 63;
} else {
return 0;
}
}

DO_ZPZI(sve_asr_zpzi_b, int8_t, H1, DO_SHR)
DO_ZPZI(sve_asr_zpzi_h, int16_t, H1_2, DO_SHR)
DO_ZPZI(sve_asr_zpzi_s, int32_t, H1_4, DO_SHR)
Expand All @@ -1888,12 +1899,51 @@ DO_ZPZI(sve_asrd_h, int16_t, H1_2, DO_ASRD)
DO_ZPZI(sve_asrd_s, int32_t, H1_4, DO_ASRD)
DO_ZPZI_D(sve_asrd_d, int64_t, DO_ASRD)

#undef DO_SHR
#undef DO_SHL
#undef DO_ASRD
#undef DO_ZPZI
#undef DO_ZPZI_D

#define DO_SHRNB(NAME, TYPEW, TYPEN, OP) \
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
{ \
intptr_t i, opr_sz = simd_oprsz(desc); \
int shift = simd_data(desc); \
for (i = 0; i < opr_sz; i += sizeof(TYPEW)) { \
TYPEW nn = *(TYPEW *)(vn + i); \
*(TYPEW *)(vd + i) = (TYPEN)OP(nn, shift); \
} \
}

#define DO_SHRNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
{ \
intptr_t i, opr_sz = simd_oprsz(desc); \
int shift = simd_data(desc); \
for (i = 0; i < opr_sz; i += sizeof(TYPEW)) { \
TYPEW nn = *(TYPEW *)(vn + HW(i)); \
*(TYPEN *)(vd + HN(i + sizeof(TYPEN))) = OP(nn, shift); \
} \
}

DO_SHRNB(sve2_shrnb_h, uint16_t, uint8_t, DO_SHR)
DO_SHRNB(sve2_shrnb_s, uint32_t, uint16_t, DO_SHR)
DO_SHRNB(sve2_shrnb_d, uint64_t, uint32_t, DO_SHR)

DO_SHRNT(sve2_shrnt_h, uint16_t, uint8_t, H1_2, H1, DO_SHR)
DO_SHRNT(sve2_shrnt_s, uint32_t, uint16_t, H1_4, H1_2, DO_SHR)
DO_SHRNT(sve2_shrnt_d, uint64_t, uint32_t, , H1_4, DO_SHR)

DO_SHRNB(sve2_rshrnb_h, uint16_t, uint8_t, do_urshr)
DO_SHRNB(sve2_rshrnb_s, uint32_t, uint16_t, do_urshr)
DO_SHRNB(sve2_rshrnb_d, uint64_t, uint32_t, do_urshr)

DO_SHRNT(sve2_rshrnt_h, uint16_t, uint8_t, H1_2, H1, do_urshr)
DO_SHRNT(sve2_rshrnt_s, uint32_t, uint16_t, H1_4, H1_2, do_urshr)
DO_SHRNT(sve2_rshrnt_d, uint64_t, uint32_t, , H1_4, do_urshr)

#undef DO_SHRNB
#undef DO_SHRNT

/* Fully general four-operand expander, controlled by a predicate.
*/
#define DO_ZPZZZ(NAME, TYPE, H, OP) \
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160 changes: 160 additions & 0 deletions target/arm/translate-sve.c
View file
Expand Up @@ -6698,6 +6698,166 @@ static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a)
return do_sve2_narrow_extract(s, a, ops);
}

static bool do_sve2_shr_narrow(DisasContext *s, arg_rri_esz *a,
const GVecGen2i ops[3])
{
if (a->esz < 0 || a->esz > MO_32 || !dc_isar_feature(aa64_sve2, s)) {
return false;
}
assert(a->imm > 0 && a->imm <= (8 << a->esz));
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vsz, vsz, a->imm, &ops[a->esz]);
}
return true;
}

static void gen_shrnb_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr)
{
int halfbits = 4 << vece;
uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits));

tcg_gen_shri_i64(d, n, shr);
tcg_gen_andi_i64(d, d, mask);
}

static void gen_shrnb16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
gen_shrnb_i64(MO_16, d, n, shr);
}

static void gen_shrnb32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
gen_shrnb_i64(MO_32, d, n, shr);
}

static void gen_shrnb64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
gen_shrnb_i64(MO_64, d, n, shr);
}

static void gen_shrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
int halfbits = 4 << vece;
uint64_t mask = MAKE_64BIT_MASK(0, halfbits);

tcg_gen_shri_vec(vece, n, n, shr);
tcg_gen_dupi_vec(vece, t, mask);
tcg_gen_and_vec(vece, d, n, t);
tcg_temp_free_vec(t);
}

static bool trans_SHRNB(DisasContext *s, arg_rri_esz *a)
{
static const TCGOpcode vec_list[] = { INDEX_op_shri_vec, 0 };
static const GVecGen2i ops[3] = {
{ .fni8 = gen_shrnb16_i64,
.fniv = gen_shrnb_vec,
.opt_opc = vec_list,
.fno = gen_helper_sve2_shrnb_h,
.vece = MO_16 },
{ .fni8 = gen_shrnb32_i64,
.fniv = gen_shrnb_vec,
.opt_opc = vec_list,
.fno = gen_helper_sve2_shrnb_s,
.vece = MO_32 },
{ .fni8 = gen_shrnb64_i64,
.fniv = gen_shrnb_vec,
.opt_opc = vec_list,
.fno = gen_helper_sve2_shrnb_d,
.vece = MO_64 },
};
return do_sve2_shr_narrow(s, a, ops);
}

static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr)
{
int halfbits = 4 << vece;
uint64_t mask = dup_const(vece, MAKE_64BIT_MASK(0, halfbits));

tcg_gen_shli_i64(n, n, halfbits - shr);
tcg_gen_andi_i64(n, n, ~mask);
tcg_gen_andi_i64(d, d, mask);
tcg_gen_or_i64(d, d, n);
}

static void gen_shrnt16_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
gen_shrnt_i64(MO_16, d, n, shr);
}

static void gen_shrnt32_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
gen_shrnt_i64(MO_32, d, n, shr);
}

static void gen_shrnt64_i64(TCGv_i64 d, TCGv_i64 n, int64_t shr)
{
tcg_gen_shri_i64(n, n, shr);
tcg_gen_deposit_i64(d, d, n, 32, 32);
}

static void gen_shrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
int halfbits = 4 << vece;
uint64_t mask = MAKE_64BIT_MASK(0, halfbits);

tcg_gen_shli_vec(vece, n, n, halfbits - shr);
tcg_gen_dupi_vec(vece, t, mask);
tcg_gen_bitsel_vec(vece, d, t, d, n);
tcg_temp_free_vec(t);
}

static bool trans_SHRNT(DisasContext *s, arg_rri_esz *a)
{
static const TCGOpcode vec_list[] = { INDEX_op_shli_vec, 0 };
static const GVecGen2i ops[3] = {
{ .fni8 = gen_shrnt16_i64,
.fniv = gen_shrnt_vec,
.opt_opc = vec_list,
.load_dest = true,
.fno = gen_helper_sve2_shrnt_h,
.vece = MO_16 },
{ .fni8 = gen_shrnt32_i64,
.fniv = gen_shrnt_vec,
.opt_opc = vec_list,
.load_dest = true,
.fno = gen_helper_sve2_shrnt_s,
.vece = MO_32 },
{ .fni8 = gen_shrnt64_i64,
.fniv = gen_shrnt_vec,
.opt_opc = vec_list,
.load_dest = true,
.fno = gen_helper_sve2_shrnt_d,
.vece = MO_64 },
};
return do_sve2_shr_narrow(s, a, ops);
}

static bool trans_RSHRNB(DisasContext *s, arg_rri_esz *a)
{
static const GVecGen2i ops[3] = {
{ .fno = gen_helper_sve2_rshrnb_h },
{ .fno = gen_helper_sve2_rshrnb_s },
{ .fno = gen_helper_sve2_rshrnb_d },
};
return do_sve2_shr_narrow(s, a, ops);
}

static bool trans_RSHRNT(DisasContext *s, arg_rri_esz *a)
{
static const GVecGen2i ops[3] = {
{ .fno = gen_helper_sve2_rshrnt_h },
{ .fno = gen_helper_sve2_rshrnt_s },
{ .fno = gen_helper_sve2_rshrnt_d },
};
return do_sve2_shr_narrow(s, a, ops);
}

static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_4_ptr *fn)
{
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