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target/loongarch: Use {set/get}_gpr replace to cpu_fpr
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Introduce set_fpr() and get_fpr() and remove cpu_fpr.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-44-gaosong@loongson.cn>
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@gaosong-loongson
gaosong-loongson committed May 6, 2023
1 parent 29bb5d7 commit 4854bbb
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Showing 5 changed files with 129 additions and 43 deletions.
72 changes: 60 additions & 12 deletions target/loongarch/insn_trans/trans_farith.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -17,18 +17,29 @@
static bool gen_fff(DisasContext *ctx, arg_fff *a,
void (*func)(TCGv, TCGv_env, TCGv, TCGv))
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src1 = get_fpr(ctx, a->fj);
TCGv src2 = get_fpr(ctx, a->fk);

CHECK_FPE;

func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
func(dest, cpu_env, src1, src2);
set_fpr(a->fd, dest);

return true;
}

static bool gen_ff(DisasContext *ctx, arg_ff *a,
void (*func)(TCGv, TCGv_env, TCGv))
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);

CHECK_FPE;

func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
func(dest, cpu_env, src);
set_fpr(a->fd, dest);

return true;
}

Expand All @@ -37,61 +48,98 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
int flag)
{
TCGv_i32 tflag = tcg_constant_i32(flag);
TCGv dest = get_fpr(ctx, a->fd);
TCGv src1 = get_fpr(ctx, a->fj);
TCGv src2 = get_fpr(ctx, a->fk);
TCGv src3 = get_fpr(ctx, a->fa);

CHECK_FPE;

func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
func(dest, cpu_env, src1, src2, src3, tflag);
set_fpr(a->fd, dest);

return true;
}

static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src1 = get_fpr(ctx, a->fk);
TCGv src2 = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
tcg_gen_deposit_i64(dest, src1, src2, 0, 31);
set_fpr(a->fd, dest);

return true;
}

static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src1 = get_fpr(ctx, a->fk);
TCGv src2 = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
tcg_gen_deposit_i64(dest, src1, src2, 0, 63);
set_fpr(a->fd, dest);

return true;
}

static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));
gen_nanbox_s(dest, dest);
set_fpr(a->fd, dest);

return true;
}

static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));
set_fpr(a->fd, dest);

return true;
}

static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
tcg_gen_xori_i64(dest, src, 0x80000000);
gen_nanbox_s(dest, dest);
set_fpr(a->fd, dest);

return true;
}

static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
{
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);

CHECK_FPE;

tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
tcg_gen_xori_i64(dest, src, 0x8000000000000000LL);
set_fpr(a->fd, dest);

return true;
}

Expand Down
12 changes: 8 additions & 4 deletions target/loongarch/insn_trans/trans_fcmp.c.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,35 +25,39 @@ static uint32_t get_fcmp_flags(int cond)

static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
{
TCGv var;
TCGv var, src1, src2;
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);

CHECK_FPE;

var = tcg_temp_new();
src1 = get_fpr(ctx, a->fj);
src2 = get_fpr(ctx, a->fk);
fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1);

fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
fn(var, cpu_env, src1, src2, tcg_constant_i32(flags));

tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
return true;
}

static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
{
TCGv var;
TCGv var, src1, src2;
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);

CHECK_FPE;

var = tcg_temp_new();
src1 = get_fpr(ctx, a->fj);
src2 = get_fpr(ctx, a->fk);
fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1);

fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
fn(var, cpu_env, src1, src2, tcg_constant_i32(flags));

tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
return true;
Expand Down
37 changes: 25 additions & 12 deletions target/loongarch/insn_trans/trans_fmemory.c.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop)
static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv dest = get_fpr(ctx, a->fd);

CHECK_FPE;

Expand All @@ -22,15 +23,17 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
addr = temp;
}

tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);

return true;
}

static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src = get_fpr(ctx, a->fd);

CHECK_FPE;

Expand All @@ -40,22 +43,25 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
addr = temp;
}

tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);

return true;
}

static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv dest = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);

return true;
}
Expand All @@ -64,13 +70,14 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv src3 = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);

return true;
}
Expand All @@ -79,15 +86,17 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv dest = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);

return true;
}
Expand All @@ -96,14 +105,15 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv src3 = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);

return true;
}
Expand All @@ -112,15 +122,17 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv dest = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);

return true;
}
Expand All @@ -129,14 +141,15 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv src3 = get_fpr(ctx, a->fd);
TCGv addr;

CHECK_FPE;

addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);

return true;
}
Expand Down

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