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ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs
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This device appears in other SoCs as well not just in 405 ones

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@zbalaton @dgibson
zbalaton authored and dgibson committed Sep 7, 2017
1 parent f5509b6 commit 517284a
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Showing 3 changed files with 266 additions and 263 deletions.
263 changes: 0 additions & 263 deletions hw/ppc/ppc405_uc.c
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Expand Up @@ -42,7 +42,6 @@
//#define DEBUG_OCM
//#define DEBUG_I2C
//#define DEBUG_GPT
//#define DEBUG_MAL
//#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL

Expand Down Expand Up @@ -1512,268 +1511,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}

/*****************************************************************************/
/* MAL */
enum {
MAL0_CFG = 0x180,
MAL0_ESR = 0x181,
MAL0_IER = 0x182,
MAL0_TXCASR = 0x184,
MAL0_TXCARR = 0x185,
MAL0_TXEOBISR = 0x186,
MAL0_TXDEIR = 0x187,
MAL0_RXCASR = 0x190,
MAL0_RXCARR = 0x191,
MAL0_RXEOBISR = 0x192,
MAL0_RXDEIR = 0x193,
MAL0_TXCTP0R = 0x1A0,
MAL0_TXCTP1R = 0x1A1,
MAL0_TXCTP2R = 0x1A2,
MAL0_TXCTP3R = 0x1A3,
MAL0_RXCTP0R = 0x1C0,
MAL0_RXCTP1R = 0x1C1,
MAL0_RCBS0 = 0x1E0,
MAL0_RCBS1 = 0x1E1,
};

typedef struct ppc40x_mal_t ppc40x_mal_t;
struct ppc40x_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
uint32_t ier;
uint32_t txcasr;
uint32_t txcarr;
uint32_t txeobisr;
uint32_t txdeir;
uint32_t rxcasr;
uint32_t rxcarr;
uint32_t rxeobisr;
uint32_t rxdeir;
uint32_t txctpr[4];
uint32_t rxctpr[2];
uint32_t rcbs[2];
};

static void ppc40x_mal_reset (void *opaque);

static uint32_t dcr_read_mal (void *opaque, int dcrn)
{
ppc40x_mal_t *mal;
uint32_t ret;

mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
break;
case MAL0_ESR:
ret = mal->esr;
break;
case MAL0_IER:
ret = mal->ier;
break;
case MAL0_TXCASR:
ret = mal->txcasr;
break;
case MAL0_TXCARR:
ret = mal->txcarr;
break;
case MAL0_TXEOBISR:
ret = mal->txeobisr;
break;
case MAL0_TXDEIR:
ret = mal->txdeir;
break;
case MAL0_RXCASR:
ret = mal->rxcasr;
break;
case MAL0_RXCARR:
ret = mal->rxcarr;
break;
case MAL0_RXEOBISR:
ret = mal->rxeobisr;
break;
case MAL0_RXDEIR:
ret = mal->rxdeir;
break;
case MAL0_TXCTP0R:
ret = mal->txctpr[0];
break;
case MAL0_TXCTP1R:
ret = mal->txctpr[1];
break;
case MAL0_TXCTP2R:
ret = mal->txctpr[2];
break;
case MAL0_TXCTP3R:
ret = mal->txctpr[3];
break;
case MAL0_RXCTP0R:
ret = mal->rxctpr[0];
break;
case MAL0_RXCTP1R:
ret = mal->rxctpr[1];
break;
case MAL0_RCBS0:
ret = mal->rcbs[0];
break;
case MAL0_RCBS1:
ret = mal->rcbs[1];
break;
default:
ret = 0;
break;
}

return ret;
}

static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
{
ppc40x_mal_t *mal;
int idx;

mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000)
ppc40x_mal_reset(mal);
mal->cfg = val & 0x00FFC087;
break;
case MAL0_ESR:
/* Read/clear */
mal->esr &= ~val;
break;
case MAL0_IER:
mal->ier = val & 0x0000001F;
break;
case MAL0_TXCASR:
mal->txcasr = val & 0xF0000000;
break;
case MAL0_TXCARR:
mal->txcarr = val & 0xF0000000;
break;
case MAL0_TXEOBISR:
/* Read/clear */
mal->txeobisr &= ~val;
break;
case MAL0_TXDEIR:
/* Read/clear */
mal->txdeir &= ~val;
break;
case MAL0_RXCASR:
mal->rxcasr = val & 0xC0000000;
break;
case MAL0_RXCARR:
mal->rxcarr = val & 0xC0000000;
break;
case MAL0_RXEOBISR:
/* Read/clear */
mal->rxeobisr &= ~val;
break;
case MAL0_RXDEIR:
/* Read/clear */
mal->rxdeir &= ~val;
break;
case MAL0_TXCTP0R:
idx = 0;
goto update_tx_ptr;
case MAL0_TXCTP1R:
idx = 1;
goto update_tx_ptr;
case MAL0_TXCTP2R:
idx = 2;
goto update_tx_ptr;
case MAL0_TXCTP3R:
idx = 3;
update_tx_ptr:
mal->txctpr[idx] = val;
break;
case MAL0_RXCTP0R:
idx = 0;
goto update_rx_ptr;
case MAL0_RXCTP1R:
idx = 1;
update_rx_ptr:
mal->rxctpr[idx] = val;
break;
case MAL0_RCBS0:
idx = 0;
goto update_rx_size;
case MAL0_RCBS1:
idx = 1;
update_rx_size:
mal->rcbs[idx] = val & 0x000000FF;
break;
}
}

static void ppc40x_mal_reset (void *opaque)
{
ppc40x_mal_t *mal;

mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
mal->rxcasr = 0x00000000;
mal->rxdeir = 0x00000000;
mal->rxeobisr = 0x00000000;
mal->txcasr = 0x00000000;
mal->txdeir = 0x00000000;
mal->txeobisr = 0x00000000;
}

static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;

mal = g_malloc0(sizeof(ppc40x_mal_t));
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_ESR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_IER,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCASR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCARR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXEOBISR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXDEIR,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP2R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_TXCTP3R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP0R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RXCTP1R,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS0,
mal, &dcr_read_mal, &dcr_write_mal);
ppc_dcr_register(env, MAL0_RCBS1,
mal, &dcr_read_mal, &dcr_write_mal);
}

/*****************************************************************************/
/* SPR */
void ppc40x_core_reset(PowerPCCPU *cpu)
Expand Down

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