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Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into…
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… staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)

# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210711:
  dp8393x: don't force 32-bit register access
  dp8393x: Rewrite dp8393x_get() / dp8393x_put()
  dp8393x: Store CAM registers as 16-bit
  dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
  dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
  dp8393x: fix CAM descriptor entry index
  target/mips: Rewrite UHI errno_mips() using switch statement
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
  hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
  hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@pm215
pm215 committed Jul 12, 2021
2 parents bd38ae2 + 39d9919 commit 552fda4
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Showing 10 changed files with 526 additions and 157 deletions.
2 changes: 1 addition & 1 deletion MAINTAINERS
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Expand Up @@ -1304,7 +1304,7 @@ S: Maintained
F: hw/ppc/prep.c
F: hw/ppc/prep_systemio.c
F: hw/ppc/rs6000_mc.c
F: hw/pci-host/prep.[hc]
F: hw/pci-host/raven.c
F: hw/isa/i82378.c
F: hw/isa/pc87312.c
F: hw/dma/i82374.c
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208 changes: 88 additions & 120 deletions hw/net/dp8393x.c
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Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion hw/pci-host/Kconfig
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Expand Up @@ -6,7 +6,7 @@ config XEN_IGD_PASSTHROUGH
default y
depends on XEN && PCI_I440FX

config PREP_PCI
config RAVEN_PCI
bool
select PCI
select OR_IRQ
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2 changes: 1 addition & 1 deletion hw/pci-host/meson.build
View file
Expand Up @@ -13,7 +13,7 @@ pci_ss.add(when: 'CONFIG_REMOTE_PCIHOST', if_true: files('remote.c'))
pci_ss.add(when: 'CONFIG_SH_PCI', if_true: files('sh_pci.c'))

# PPC devices
pci_ss.add(when: 'CONFIG_PREP_PCI', if_true: files('prep.c'))
pci_ss.add(when: 'CONFIG_RAVEN_PCI', if_true: files('raven.c'))
pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
# NewWorld PowerMac
pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))
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11 changes: 7 additions & 4 deletions hw/pci-host/prep.c → hw/pci-host/raven.c
View file
Expand Up @@ -81,6 +81,8 @@ struct PRePPCIState {

#define BIOS_SIZE (1 * MiB)

#define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */

static inline uint32_t raven_pci_io_config(hwaddr addr)
{
int i;
Expand Down Expand Up @@ -158,7 +160,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr,
uint8_t buf[4];

addr = raven_io_address(s, addr);
address_space_read(&s->pci_io_as, addr + 0x80000000,
address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
MEMTXATTRS_UNSPECIFIED, buf, size);

if (size == 1) {
Expand Down Expand Up @@ -190,7 +192,7 @@ static void raven_io_write(void *opaque, hwaddr addr,
g_assert_not_reached();
}

address_space_write(&s->pci_io_as, addr + 0x80000000,
address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
MEMTXATTRS_UNSPECIFIED, buf, size);
}

Expand Down Expand Up @@ -293,8 +295,9 @@ static void raven_pcihost_initfn(Object *obj)
address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");

/* CPU address space */
memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
&s->pci_io);
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
&s->pci_io_non_contiguous, 1);
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
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2 changes: 1 addition & 1 deletion hw/ppc/Kconfig
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Expand Up @@ -85,7 +85,7 @@ config PREP
imply PCI_DEVICES
imply TEST_DEVICES
select CS4231A
select PREP_PCI
select RAVEN_PCI
select I82378
select LSI_SCSI_PCI
select M48T59
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24 changes: 9 additions & 15 deletions target/mips/tcg/sysemu/mips-semi.c
View file
Expand Up @@ -74,25 +74,19 @@ enum UHIOpenFlags {
UHIOpen_EXCL = 0x800
};

/* Errno values taken from asm-mips/errno.h */
static const uint16_t host_to_mips_errno[] = {
[ENAMETOOLONG] = 78,
static int errno_mips(int host_errno)
{
/* Errno values taken from asm-mips/errno.h */
switch (host_errno) {
case 0: return 0;
case ENAMETOOLONG: return 78;
#ifdef EOVERFLOW
[EOVERFLOW] = 79,
case EOVERFLOW: return 79;
#endif
#ifdef ELOOP
[ELOOP] = 90,
case ELOOP: return 90;
#endif
};

static int errno_mips(int err)
{
if (err < 0 || err >= ARRAY_SIZE(host_to_mips_errno)) {
return EINVAL;
} else if (host_to_mips_errno[err]) {
return host_to_mips_errno[err];
} else {
return err;
default: return EINVAL;
}
}

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16 changes: 2 additions & 14 deletions target/mips/tcg/translate.c
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Expand Up @@ -1179,7 +1179,6 @@ enum {

enum {
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};

Expand Down Expand Up @@ -15166,11 +15165,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
}
}

static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
}

static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
Expand Down Expand Up @@ -16069,14 +16063,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
}
case OPC_MDMX:
/* MDMX: Not implemented. */
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS_R6);
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34 changes: 34 additions & 0 deletions target/mips/tcg/tx79.decode
View file
Expand Up @@ -13,6 +13,8 @@

&rtype rs rt rd sa

&itype base rt offset

###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
Expand All @@ -22,18 +24,50 @@
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0

@ldst ...... base:5 rt:5 offset:16 &itype

###########################################################################

MFHI1 011100 0000000000 ..... 00000 010000 @rd
MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs

# MMI0

PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
PCGTW 011100 ..... ..... ..... 00010 001000 @rs_rt_rd
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd
PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd
PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd

# MMI1

PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd
PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd
PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd
PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd

# MMI2

PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd

# MMI3

PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd

# SPECIAL

LQ 011110 ..... ..... ................ @ldst
SQ 011111 ..... ..... ................ @ldst

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