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This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out. The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode. This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations. The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller). Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,152 @@ | ||
| /* | ||
| * Aspeed PECI Controller | ||
| * | ||
| * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com) | ||
| * | ||
| * This code is licensed under the GPL version 2 or later. See the COPYING | ||
| * file in the top-level directory. | ||
| */ | ||
|
|
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| #include "qemu/osdep.h" | ||
| #include "qemu/log.h" | ||
| #include "hw/irq.h" | ||
| #include "hw/misc/aspeed_peci.h" | ||
| #include "hw/registerfields.h" | ||
| #include "trace.h" | ||
|
|
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| #define ASPEED_PECI_CC_RSP_SUCCESS (0x40U) | ||
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| /* Command Register */ | ||
| REG32(PECI_CMD, 0x08) | ||
| FIELD(PECI_CMD, FIRE, 0, 1) | ||
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| /* Interrupt Control Register */ | ||
| REG32(PECI_INT_CTRL, 0x18) | ||
|
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| /* Interrupt Status Register */ | ||
| REG32(PECI_INT_STS, 0x1C) | ||
| FIELD(PECI_INT_STS, CMD_DONE, 0, 1) | ||
|
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| /* Rx/Tx Data Buffer Registers */ | ||
| REG32(PECI_WR_DATA0, 0x20) | ||
| REG32(PECI_RD_DATA0, 0x30) | ||
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| static void aspeed_peci_raise_interrupt(AspeedPECIState *s, uint32_t status) | ||
| { | ||
| trace_aspeed_peci_raise_interrupt(s->regs[R_PECI_INT_CTRL], status); | ||
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| s->regs[R_PECI_INT_STS] = s->regs[R_PECI_INT_CTRL] & status; | ||
| if (!s->regs[R_PECI_INT_STS]) { | ||
| return; | ||
| } | ||
| qemu_irq_raise(s->irq); | ||
| } | ||
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| static uint64_t aspeed_peci_read(void *opaque, hwaddr offset, unsigned size) | ||
| { | ||
| AspeedPECIState *s = ASPEED_PECI(opaque); | ||
| uint64_t data; | ||
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| if (offset >= ASPEED_PECI_NR_REGS << 2) { | ||
| qemu_log_mask(LOG_GUEST_ERROR, | ||
| "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | ||
| __func__, offset); | ||
| return 0; | ||
| } | ||
| data = s->regs[offset >> 2]; | ||
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| trace_aspeed_peci_read(offset, data); | ||
| return data; | ||
| } | ||
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| static void aspeed_peci_write(void *opaque, hwaddr offset, uint64_t data, | ||
| unsigned size) | ||
| { | ||
| AspeedPECIState *s = ASPEED_PECI(opaque); | ||
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| trace_aspeed_peci_write(offset, data); | ||
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| if (offset >= ASPEED_PECI_NR_REGS << 2) { | ||
| qemu_log_mask(LOG_GUEST_ERROR, | ||
| "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | ||
| __func__, offset); | ||
| return; | ||
| } | ||
|
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| switch (offset) { | ||
| case A_PECI_INT_STS: | ||
| s->regs[R_PECI_INT_STS] &= ~data; | ||
| if (!s->regs[R_PECI_INT_STS]) { | ||
| qemu_irq_lower(s->irq); | ||
| } | ||
| break; | ||
| case A_PECI_CMD: | ||
| /* | ||
| * Only the FIRE bit is writable. Once the command is complete, it | ||
| * should be cleared. Since we complete the command immediately, the | ||
| * value is not stored in the register array. | ||
| */ | ||
| if (!FIELD_EX32(data, PECI_CMD, FIRE)) { | ||
| break; | ||
| } | ||
| if (s->regs[R_PECI_INT_STS]) { | ||
| qemu_log_mask(LOG_GUEST_ERROR, "%s: Interrupt status must be " | ||
| "cleared before firing another command: 0x%08x\n", | ||
| __func__, s->regs[R_PECI_INT_STS]); | ||
| break; | ||
| } | ||
| s->regs[R_PECI_RD_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS; | ||
| s->regs[R_PECI_WR_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS; | ||
| aspeed_peci_raise_interrupt(s, | ||
| FIELD_DP32(0, PECI_INT_STS, CMD_DONE, 1)); | ||
| break; | ||
| default: | ||
| s->regs[offset / sizeof(s->regs[0])] = data; | ||
| break; | ||
| } | ||
| } | ||
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| static const MemoryRegionOps aspeed_peci_ops = { | ||
| .read = aspeed_peci_read, | ||
| .write = aspeed_peci_write, | ||
| .endianness = DEVICE_LITTLE_ENDIAN, | ||
| }; | ||
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| static void aspeed_peci_realize(DeviceState *dev, Error **errp) | ||
| { | ||
| AspeedPECIState *s = ASPEED_PECI(dev); | ||
| SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
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| memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_peci_ops, s, | ||
| TYPE_ASPEED_PECI, 0x1000); | ||
| sysbus_init_mmio(sbd, &s->mmio); | ||
| sysbus_init_irq(sbd, &s->irq); | ||
| } | ||
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| static void aspeed_peci_reset(DeviceState *dev) | ||
| { | ||
| AspeedPECIState *s = ASPEED_PECI(dev); | ||
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| memset(s->regs, 0, sizeof(s->regs)); | ||
| } | ||
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| static void aspeed_peci_class_init(ObjectClass *klass, void *data) | ||
| { | ||
| DeviceClass *dc = DEVICE_CLASS(klass); | ||
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| dc->realize = aspeed_peci_realize; | ||
| dc->reset = aspeed_peci_reset; | ||
| dc->desc = "Aspeed PECI Controller"; | ||
| } | ||
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| static const TypeInfo aspeed_peci_types[] = { | ||
| { | ||
| .name = TYPE_ASPEED_PECI, | ||
| .parent = TYPE_SYS_BUS_DEVICE, | ||
| .instance_size = sizeof(AspeedPECIState), | ||
| .class_init = aspeed_peci_class_init, | ||
| .abstract = false, | ||
| }, | ||
| }; | ||
|
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| DEFINE_TYPES(aspeed_peci_types); |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,29 @@ | ||
| /* | ||
| * Aspeed PECI Controller | ||
| * | ||
| * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com) | ||
| * | ||
| * This code is licensed under the GPL version 2 or later. See the COPYING | ||
| * file in the top-level directory. | ||
| */ | ||
|
|
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| #ifndef ASPEED_PECI_H | ||
| #define ASPEED_PECI_H | ||
|
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| #include "hw/sysbus.h" | ||
|
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| #define ASPEED_PECI_NR_REGS ((0xFC + 4) >> 2) | ||
| #define TYPE_ASPEED_PECI "aspeed.peci" | ||
| OBJECT_DECLARE_SIMPLE_TYPE(AspeedPECIState, ASPEED_PECI); | ||
|
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| struct AspeedPECIState { | ||
| /* <private> */ | ||
| SysBusDevice parent; | ||
|
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| MemoryRegion mmio; | ||
| qemu_irq irq; | ||
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| uint32_t regs[ASPEED_PECI_NR_REGS]; | ||
| }; | ||
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| #endif |