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Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
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/* | ||
* ARMv7M CPU object | ||
* | ||
* Copyright (c) 2017 Linaro Ltd | ||
* Written by Peter Maydell <peter.maydell@linaro.org> | ||
* | ||
* This code is licensed under the GPL version 2 or later. | ||
*/ | ||
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#ifndef HW_ARM_ARMV7M_H | ||
#define HW_ARM_ARMV7M_H | ||
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#include "hw/sysbus.h" | ||
#include "hw/arm/armv7m_nvic.h" | ||
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#define TYPE_BITBAND "ARM,bitband-memory" | ||
#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | ||
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typedef struct { | ||
/*< private >*/ | ||
SysBusDevice parent_obj; | ||
/*< public >*/ | ||
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MemoryRegion iomem; | ||
uint32_t base; | ||
} BitBandState; | ||
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#define TYPE_ARMV7M "armv7m" | ||
#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M) | ||
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#define ARMV7M_NUM_BITBANDS 2 | ||
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/* ARMv7M container object. | ||
* + Unnamed GPIO input lines: external IRQ lines for the NVIC | ||
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ | ||
* + Property "cpu-model": CPU model to instantiate | ||
* + Property "num-irq": number of external IRQ lines | ||
*/ | ||
typedef struct ARMv7MState { | ||
/*< private >*/ | ||
SysBusDevice parent_obj; | ||
/*< public >*/ | ||
NVICState nvic; | ||
BitBandState bitband[ARMV7M_NUM_BITBANDS]; | ||
ARMCPU *cpu; | ||
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/* Properties */ | ||
char *cpu_model; | ||
} ARMv7MState; | ||
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#endif |