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target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
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The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-9-f4bug@amsat.org>
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@philmd
philmd committed Jan 14, 2021
1 parent 959c5da commit 63af5b9
Showing 1 changed file with 28 additions and 29 deletions.
57 changes: 28 additions & 29 deletions target/mips/translate.c
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Expand Up @@ -28614,7 +28614,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
tcg_temp_free_i64(t1);
}

static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
Expand Down Expand Up @@ -28659,7 +28659,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
ctx->hflags |= MIPS_HFLAG_BDS32;
}

static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
uint8_t i8 = (ctx->opcode >> 16) & 0xff;
Expand Down Expand Up @@ -28717,7 +28717,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(ti8);
}

static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_i5(DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
Expand Down Expand Up @@ -28790,7 +28790,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(timm);
}

static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_bit(DisasContext *ctx)
{
#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
Expand Down Expand Up @@ -28874,7 +28874,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tws);
}

static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
Expand Down Expand Up @@ -29856,7 +29856,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}

static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
uint8_t source = (ctx->opcode >> 11) & 0x1f;
Expand Down Expand Up @@ -29888,8 +29888,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tsr);
}

static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
uint32_t n)
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
Expand Down Expand Up @@ -29999,7 +29998,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
tcg_temp_free_i32(tdf);
}

static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
uint32_t df = 0, n = 0;
Expand All @@ -30018,17 +30017,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
df = DF_DOUBLE;
} else if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
gen_msa_elm_3e(env, ctx);
gen_msa_elm_3e(ctx);
return;
} else {
gen_reserved_instruction(ctx);
return;
}

gen_msa_elm_df(env, ctx, df, n);
gen_msa_elm_df(ctx, df, n);
}

static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_3rf(DisasContext *ctx)
{
#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t df = (ctx->opcode >> 21) & 0x1;
Expand Down Expand Up @@ -30186,7 +30185,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}

static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
Expand Down Expand Up @@ -30270,7 +30269,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}

static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
Expand Down Expand Up @@ -30341,7 +30340,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}

static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
Expand Down Expand Up @@ -30384,7 +30383,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(twt);
}

static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa_vec(DisasContext *ctx)
{
switch (MASK_MSA_VEC(ctx->opcode)) {
case OPC_AND_V:
Expand All @@ -30394,13 +30393,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
case OPC_BMNZ_V:
case OPC_BMZ_V:
case OPC_BSEL_V:
gen_msa_vec_v(env, ctx);
gen_msa_vec_v(ctx);
break;
case OPC_MSA_2R:
gen_msa_2r(env, ctx);
gen_msa_2r(ctx);
break;
case OPC_MSA_2RF:
gen_msa_2rf(env, ctx);
gen_msa_2rf(ctx);
break;
default:
MIPS_INVAL("MSA instruction");
Expand All @@ -30409,7 +30408,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
}
}

static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;

Expand All @@ -30419,15 +30418,15 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_I8_00:
case OPC_MSA_I8_01:
case OPC_MSA_I8_02:
gen_msa_i8(env, ctx);
gen_msa_i8(ctx);
break;
case OPC_MSA_I5_06:
case OPC_MSA_I5_07:
gen_msa_i5(env, ctx);
gen_msa_i5(ctx);
break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
gen_msa_bit(env, ctx);
gen_msa_bit(ctx);
break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
Expand All @@ -30438,18 +30437,18 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_3R_13:
case OPC_MSA_3R_14:
case OPC_MSA_3R_15:
gen_msa_3r(env, ctx);
gen_msa_3r(ctx);
break;
case OPC_MSA_ELM:
gen_msa_elm(env, ctx);
gen_msa_elm(ctx);
break;
case OPC_MSA_3RF_1A:
case OPC_MSA_3RF_1B:
case OPC_MSA_3RF_1C:
gen_msa_3rf(env, ctx);
gen_msa_3rf(ctx);
break;
case OPC_MSA_VEC:
gen_msa_vec(env, ctx);
gen_msa_vec(ctx);
break;
case OPC_LD_B:
case OPC_LD_H:
Expand Down Expand Up @@ -31043,7 +31042,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_BNZ_W:
case OPC_BNZ_D:
if (ase_msa_available(env)) {
gen_msa_branch(env, ctx, op1);
gen_msa_branch(ctx, op1);
break;
}
/* fall through */
Expand Down Expand Up @@ -31236,7 +31235,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
} else {
/* MDMX: Not implemented. */
if (ase_msa_available(env)) {
gen_msa(env, ctx);
gen_msa(ctx);
}
}
break;
Expand Down

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