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Hexagon (target/hexagon) Make generators object oriented - gen_analyz…
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…e_funcs

This patch conflicts with
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
If that series goes in first, we'll rework this patch and vice versa.

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20231210220712.491494-8-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
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@taylorsimpson @androm3da
taylorsimpson authored and androm3da committed Jan 22, 2024
1 parent c90e310 commit 66fab98
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Showing 2 changed files with 157 additions and 157 deletions.
163 changes: 6 additions & 157 deletions target/hexagon/gen_analyze_funcs.py
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Original file line number Diff line number Diff line change
Expand Up @@ -23,162 +23,6 @@
import hex_common


##
## Helpers for gen_analyze_func
##
def is_predicated(tag):
return "A_CONDEXEC" in hex_common.attribdict[tag]


def analyze_opn_old(f, tag, regtype, regid, regno):
regN = f"{regtype}{regid}N"
predicated = "true" if is_predicated(tag) else "false"
if regtype == "R":
if regid in {"ss", "tt"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
elif regid in {"dd", "ee", "xx", "yy"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif regid in {"s", "t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
elif regid in {"d", "e", "x", "y"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"s", "t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_read(ctx, {regN});\n")
elif regid in {"d", "e", "x"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_write(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "C":
if regid == "ss":
f.write(
f" const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n"
)
f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n")
elif regid == "dd":
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif regid == "s":
f.write(
f" const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n"
)
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
elif regid == "d":
f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "M":
if regid == "u":
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "V":
newv = "EXT_DFL"
if hex_common.is_new_result(tag):
newv = "EXT_NEW"
elif hex_common.is_tmp_result(tag):
newv = "EXT_TMP"
if regid in {"dd", "xx"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(
f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n"
)
elif regid in {"uu", "vv"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n")
elif regid in {"s", "u", "v", "w"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
elif regid in {"d", "x", "y"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "Q":
if regid in {"d", "e", "x"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
elif regid in {"s", "t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_qreg_read(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "G":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"ss"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "S":
if regid in {"dd"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"d"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"ss"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif regid in {"s"}:
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
hex_common.bad_register(regtype, regid)
else:
hex_common.bad_register(regtype, regid)


def analyze_opn_new(f, tag, regtype, regid, regno):
regN = f"{regtype}{regid}N"
if regtype == "N":
if regid in {"s", "t"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_read(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "P":
if regid in {"t", "u", "v"}:
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_read(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
elif regtype == "O":
if regid == "s":
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_read(ctx, {regN});\n")
else:
hex_common.bad_register(regtype, regid)
else:
hex_common.bad_register(regtype, regid)


def analyze_opn(f, tag, regtype, regid, i):
if hex_common.is_pair(regid):
analyze_opn_old(f, tag, regtype, regid, i)
elif hex_common.is_single(regid):
if hex_common.is_old_val(regtype, regid, tag):
analyze_opn_old(f, tag, regtype, regid, i)
elif hex_common.is_new_val(regtype, regid, tag):
analyze_opn_new(f, tag, regtype, regid, i)
else:
hex_common.bad_register(regtype, regid)
else:
hex_common.bad_register(regtype, regid)


##
## Generate the code to analyze the instruction
## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
Expand All @@ -203,7 +47,11 @@ def gen_analyze_func(f, tag, regs, imms):
i = 0
## Analyze all the registers
for regtype, regid in regs:
analyze_opn(f, tag, regtype, regid, i)
reg = hex_common.get_register(tag, regtype, regid)
if reg.is_written():
reg.analyze_write(f, tag, i)
else:
reg.analyze_read(f, i)
i += 1

has_generated_helper = not hex_common.skip_qemu_helper(
Expand Down Expand Up @@ -236,6 +84,7 @@ def main():
if is_idef_parser_enabled:
hex_common.read_idef_parser_enabled_file(sys.argv[5])
hex_common.calculate_attribs()
hex_common.init_registers()
tagregs = hex_common.get_tagregs()
tagimms = hex_common.get_tagimms()

Expand Down

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