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Merge tag 'pull-tricore-20230929' of https://github.com/bkoppelmann/qemu
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 into staging

- Add FTOU, CRCN, FTOHP, and HPTOF insns

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# gpg: Signature made Fri 29 Sep 2023 02:32:11 EDT
# gpg:                using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg:                issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* tag 'pull-tricore-20230929' of https://github.com/bkoppelmann/qemu:
  target/tricore: Change effective address (ea) to target_ulong
  target/tricore: Remove CSFRs from cpu.h
  tests/tcg: Reset result register after each test
  hw/tricore: Log failing test in testdevice
  tests/tcg/tricore: Extended and non-extened regs now match
  target/tricore: Fix FTOUZ being ISA v1.3.1 up
  target/tricore: Replace cpu_*_code with translator_*
  target/tricore: Swap src and dst reg for RCRR_INSERT
  target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
  target/tricore: Implement hptof insn
  target/tricore: Implement ftohp insn
  target/tricore: Clarify special case for FTOUZ insn
  target/tricore: Implement FTOU insn
  target/tricore: Correctly handle FPU RM from PSW
  target/tricore: Implement CRCN insn
  tests/tcg/tricore: Bump cpu to tc37x

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@stefanhaRH
stefanhaRH committed Oct 2, 2023
2 parents 8a9c46a + ceada00 commit 696e5d9
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Showing 15 changed files with 376 additions and 175 deletions.
4 changes: 4 additions & 0 deletions hw/tricore/tricore_testdevice.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,17 @@
*/

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "hw/tricore/tricore_testdevice.h"

static void tricore_testdevice_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
if (value != 0) {
qemu_log_mask(LOG_GUEST_ERROR, "Test %" PRIu64 " failed!\n", value);
}
exit(value);
}

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143 changes: 9 additions & 134 deletions target/tricore/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -30,150 +30,25 @@ typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
/* CSFR Register */
uint32_t PCXI;
/* Frequently accessed PSW_USB bits are stored separately for efficiency.
This contains all the other bits. Use psw_{read,write} to access
the whole PSW. */
uint32_t PSW;

/* PSW flag cache for faster execution
*/
/* PSW flag cache for faster execution */
uint32_t PSW_USB_C;
uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */

uint32_t PC;
uint32_t SYSCON;
uint32_t CPU_ID;
uint32_t CORE_ID;
uint32_t BIV;
uint32_t BTV;
uint32_t ISP;
uint32_t ICR;
uint32_t FCX;
uint32_t LCX;
uint32_t COMPAT;

/* Mem Protection Register */
uint32_t DPR0_0L;
uint32_t DPR0_0U;
uint32_t DPR0_1L;
uint32_t DPR0_1U;
uint32_t DPR0_2L;
uint32_t DPR0_2U;
uint32_t DPR0_3L;
uint32_t DPR0_3U;

uint32_t DPR1_0L;
uint32_t DPR1_0U;
uint32_t DPR1_1L;
uint32_t DPR1_1U;
uint32_t DPR1_2L;
uint32_t DPR1_2U;
uint32_t DPR1_3L;
uint32_t DPR1_3U;

uint32_t DPR2_0L;
uint32_t DPR2_0U;
uint32_t DPR2_1L;
uint32_t DPR2_1U;
uint32_t DPR2_2L;
uint32_t DPR2_2U;
uint32_t DPR2_3L;
uint32_t DPR2_3U;

uint32_t DPR3_0L;
uint32_t DPR3_0U;
uint32_t DPR3_1L;
uint32_t DPR3_1U;
uint32_t DPR3_2L;
uint32_t DPR3_2U;
uint32_t DPR3_3L;
uint32_t DPR3_3U;

uint32_t CPR0_0L;
uint32_t CPR0_0U;
uint32_t CPR0_1L;
uint32_t CPR0_1U;
uint32_t CPR0_2L;
uint32_t CPR0_2U;
uint32_t CPR0_3L;
uint32_t CPR0_3U;

uint32_t CPR1_0L;
uint32_t CPR1_0U;
uint32_t CPR1_1L;
uint32_t CPR1_1U;
uint32_t CPR1_2L;
uint32_t CPR1_2U;
uint32_t CPR1_3L;
uint32_t CPR1_3U;

uint32_t CPR2_0L;
uint32_t CPR2_0U;
uint32_t CPR2_1L;
uint32_t CPR2_1U;
uint32_t CPR2_2L;
uint32_t CPR2_2U;
uint32_t CPR2_3L;
uint32_t CPR2_3U;

uint32_t CPR3_0L;
uint32_t CPR3_0U;
uint32_t CPR3_1L;
uint32_t CPR3_1U;
uint32_t CPR3_2L;
uint32_t CPR3_2U;
uint32_t CPR3_3L;
uint32_t CPR3_3U;

uint32_t DPM0;
uint32_t DPM1;
uint32_t DPM2;
uint32_t DPM3;

uint32_t CPM0;
uint32_t CPM1;
uint32_t CPM2;
uint32_t CPM3;

/* Memory Management Registers */
uint32_t MMU_CON;
uint32_t MMU_ASI;
uint32_t MMU_TVA;
uint32_t MMU_TPA;
uint32_t MMU_TPX;
uint32_t MMU_TFA;
/* {1.3.1 only */
uint32_t BMACON;
uint32_t SMACON;
uint32_t DIEAR;
uint32_t DIETR;
uint32_t CCDIER;
uint32_t MIECON;
uint32_t PIEAR;
uint32_t PIETR;
uint32_t CCPIER;
/*} */
/* Debug Registers */
uint32_t DBGSR;
uint32_t EXEVT;
uint32_t CREVT;
uint32_t SWEVT;
uint32_t TR0EVT;
uint32_t TR1EVT;
uint32_t DMS;
uint32_t DCX;
uint32_t DBGTCR;
uint32_t CCTRL;
uint32_t CCNT;
uint32_t ICNT;
uint32_t M1CNT;
uint32_t M2CNT;
uint32_t M3CNT;
#define R(ADDR, NAME, FEATURE) uint32_t NAME;
#define A(ADDR, NAME, FEATURE) uint32_t NAME;
#define E(ADDR, NAME, FEATURE) uint32_t NAME;
#include "csfr.h.inc"
#undef R
#undef A
#undef E

/* Floating Point Registers */
float_status fp_status;

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111 changes: 111 additions & 0 deletions target/tricore/fpu_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -373,6 +373,80 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}

uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
{
float16 f_arg = make_float16(arg);
uint32_t result = 0;
int32_t flags = 0;

/*
* if we have any NAN we need to move the top 2 and lower 8 input mantissa
* bits to the top 2 and lower 8 output mantissa bits respectively.
* Softfloat on the other hand uses the top 10 mantissa bits.
*/
if (float16_is_any_nan(f_arg)) {
if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
flags |= float_flag_invalid;
}
result = 0;
result = float32_set_sign(result, f_arg >> 15);
result = deposit32(result, 23, 8, 0xff);
result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
} else {
set_flush_inputs_to_zero(0, &env->fp_status);
result = float16_to_float32(f_arg, true, &env->fp_status);
set_flush_inputs_to_zero(1, &env->fp_status);
flags = f_get_excp_flags(env);
}

if (flags) {
f_update_psw_flags(env, flags);
} else {
env->FPU_FS = 0;
}

return result;
}

uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
uint32_t result = 0;
int32_t flags = 0;

/*
* if we have any NAN we need to move the top 2 and lower 8 input mantissa
* bits to the top 2 and lower 8 output mantissa bits respectively.
* Softfloat on the other hand uses the top 10 mantissa bits.
*/
if (float32_is_any_nan(f_arg)) {
if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
flags |= float_flag_invalid;
}
result = float16_set_sign(result, arg >> 31);
result = deposit32(result, 10, 5, 0x1f);
result = deposit32(result, 8, 2, extract32(arg, 21, 2));
result = deposit32(result, 0, 8, extract32(arg, 0, 8));
if (extract32(result, 0, 10) == 0) {
result |= (1 << 8);
}
} else {
set_flush_to_zero(0, &env->fp_status);
result = float32_to_float16(f_arg, true, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
flags = f_get_excp_flags(env);
}

if (flags) {
f_update_psw_flags(env, flags);
} else {
env->FPU_FS = 0;
}

return result;
}

uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
{
float32 f_result;
Expand Down Expand Up @@ -429,6 +503,38 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
return result;
}

uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
uint32_t result;
int32_t flags = 0;

result = float32_to_uint32(f_arg, &env->fp_status);

flags = f_get_excp_flags(env);
if (flags & float_flag_invalid) {
flags &= ~float_flag_inexact;
if (float32_is_any_nan(f_arg)) {
result = 0;
}
/*
* we need to check arg < 0.0 before rounding as TriCore needs to raise
* float_flag_invalid as well. For instance, when we have a negative
* exponent and sign, softfloat would only raise float_flat_inexact.
*/
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
flags = float_flag_invalid;
result = 0;
}

if (flags) {
f_update_psw_flags(env, flags);
} else {
env->FPU_FS = 0;
}
return result;
}

uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
Expand All @@ -443,6 +549,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
if (float32_is_any_nan(f_arg)) {
result = 0;
}
/*
* we need to check arg < 0.0 before rounding as TriCore needs to raise
* float_flag_invalid as well. For instance, when we have a negative
* exponent and sign, softfloat would only raise float_flat_inexact.
*/
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
flags = float_flag_invalid;
result = 0;
Expand Down
19 changes: 17 additions & 2 deletions target/tricore/helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -120,16 +120,31 @@ void tricore_cpu_list(void)

void fpu_set_state(CPUTriCoreState *env)
{
set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
switch (extract32(env->PSW, 24, 2)) {
case 0:
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
break;
case 1:
set_float_rounding_mode(float_round_up, &env->fp_status);
break;
case 2:
set_float_rounding_mode(float_round_down, &env->fp_status);
break;
case 3:
set_float_rounding_mode(float_round_to_zero, &env->fp_status);
break;
}

set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
}

uint32_t psw_read(CPUTriCoreState *env)
{
/* clear all USB bits */
env->PSW &= 0x6ffffff;
env->PSW &= 0x7ffffff;
/* now set them from the cache */
env->PSW |= ((env->PSW_USB_C != 0) << 31);
env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
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4 changes: 4 additions & 0 deletions target/tricore/helper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -111,9 +111,12 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
DEF_HELPER_2(ftou, i32, env, i32)
DEF_HELPER_2(ftouz, i32, env, i32)
DEF_HELPER_2(updfl, void, env, i32)
/* dvinit */
Expand All @@ -134,6 +137,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
Expand Down

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