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Merge tag 'pull-tricore-20230928' of https://github.com/bkoppelmann/qemu
into staging - Add FTOU, CRCN, FTOHP, and HPTOF insns - Add test for arithmetic TriCore insns # -----BEGIN PGP SIGNATURE----- # # iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAmUVPVgfHGtiYXN0aWFu # QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFFzmD/9iWljlOkYEH/pe # AJXi08MAFtVxZ7b5pkv4a/oMVy+/RtqXnTLqsh3RChby0YNaY9t4ySXCDk9n1E7c # zrJ6dPzJ7MhNSOz9Hz0uHYZrY9ZVKsjr6GT/VMy1QcHm5z47gzNn0NwJ9WVImr4R # Dv80PYcMueP08LHO81tACSV0ppxcg1WgRV+onyX9BgZVbdh51JS313OvtUfvvwyC # pBxzzyZccXkLlzm0ObcEUbTCJ+fGOJ3jwHwBIEaEZFujdmBU2sM8+BTV0FgyvwH/ # 2JuM1GlKxef2lT9JInfzbwturtaKCj4uBhtw7Jvj69rQlIbal+m0AYAbr20xWCiD # DPt6UeO9xFy+2LvjxQFv3iAFSjRvdQwYTnnq/on8LQ4y+m7fZ2a0Utl8OZlj/pX8 # 0LDPspC10aSxzqBYqkjTaahzGZbZmLapV4eAwrHNHa3JnOGk45paOJFX2JnPB1gB # T2O8Mc738I1M6qPQzSMrM8y7xlRi97kUpF5BLfYUdjNpUVb03KIK9aEq74paAU+a # IZTwE7U+8jn7ZEzFwMRIu0rg+bFi1ZlMmvDZm9kbBHQwoZ5xPoyEIoITlXw4B/Kk # vg2bLz6SH+tzu9DLcoWg7FupxNE3VOtJgkGXCN2tkYoJwDE9wjVpGYJ1anW+fTZN # J8/iunffflAyaLkRh5hi5iklvHqOeA== # =3Fk7 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 28 Sep 2023 04:46:16 EDT # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Can't check signature: No public key * tag 'pull-tricore-20230928' of https://github.com/bkoppelmann/qemu: (21 commits) target/tricore: Change effective address (ea) to target_ulong target/tricore: Remove CSFRs from cpu.h tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' tests/tcg/tricore: Add test from 'max' to 'shas' tests/tcg/tricore: Add test from 'dextr' to 'lt' tests/tcg/tricore: Add test from 'and' to 'csub' tests/tcg/tricore: Add test for all arith insns up to addx tests/tcg: Reset result register after each test hw/tricore: Log failing test in testdevice tests/tcg/tricore: Extended and non-extened regs now match target/tricore: Fix FTOUZ being ISA v1.3.1 up target/tricore: Replace cpu_*_code with translator_* target/tricore: Swap src and dst reg for RCRR_INSERT target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 target/tricore: Implement hptof insn target/tricore: Implement ftohp insn target/tricore: Clarify special case for FTOUZ insn target/tricore: Implement FTOU insn target/tricore: Correctly handle FPU RM from PSW target/tricore: Implement CRCN insn ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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