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target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0
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Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Macro-ize the 5 nearly identical comparisons.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@rth7680 @pm215
rth7680 authored and pm215 committed May 14, 2020
1 parent 3f08f0b commit 69d5e2b
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Showing 3 changed files with 74 additions and 218 deletions.
22 changes: 11 additions & 11 deletions target/arm/translate-a64.c
View file
Expand Up @@ -577,14 +577,6 @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm,
is_q ? 16 : 8, vec_full_reg_size(s));
}

/* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */
static void gen_gvec_op2(DisasContext *s, bool is_q, int rd,
int rn, const GVecGen2 *gvec_op)
{
tcg_gen_gvec_2(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
}

/* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
static void gen_gvec_op3(DisasContext *s, bool is_q, int rd,
int rn, int rm, const GVecGen3 *gvec_op)
Expand Down Expand Up @@ -12310,13 +12302,21 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x8: /* CMGT, CMGE */
gen_gvec_op2(s, is_q, rd, rn, u ? &cge0_op[size] : &cgt0_op[size]);
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size);
}
return;
case 0x9: /* CMEQ, CMLE */
gen_gvec_op2(s, is_q, rd, rn, u ? &cle0_op[size] : &ceq0_op[size]);
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size);
}
return;
case 0xa: /* CMLT */
gen_gvec_op2(s, is_q, rd, rn, &clt0_op[size]);
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0xb:
if (u) { /* ABS, NEG */
Expand Down
254 changes: 52 additions & 202 deletions target/arm/translate.c
View file
Expand Up @@ -3645,204 +3645,59 @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
return 1;
}

static void gen_ceq0_i32(TCGv_i32 d, TCGv_i32 a)
{
tcg_gen_setcondi_i32(TCG_COND_EQ, d, a, 0);
tcg_gen_neg_i32(d, d);
}

static void gen_ceq0_i64(TCGv_i64 d, TCGv_i64 a)
{
tcg_gen_setcondi_i64(TCG_COND_EQ, d, a, 0);
tcg_gen_neg_i64(d, d);
}

static void gen_ceq0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
{
TCGv_vec zero = tcg_const_zeros_vec_matching(d);
tcg_gen_cmp_vec(TCG_COND_EQ, vece, d, a, zero);
tcg_temp_free_vec(zero);
}
#define GEN_CMP0(NAME, COND) \
static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \
{ \
tcg_gen_setcondi_i32(COND, d, a, 0); \
tcg_gen_neg_i32(d, d); \
} \
static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \
{ \
tcg_gen_setcondi_i64(COND, d, a, 0); \
tcg_gen_neg_i64(d, d); \
} \
static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \
{ \
TCGv_vec zero = tcg_const_zeros_vec_matching(d); \
tcg_gen_cmp_vec(COND, vece, d, a, zero); \
tcg_temp_free_vec(zero); \
} \
void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \
uint32_t opr_sz, uint32_t max_sz) \
{ \
const GVecGen2 op[4] = { \
{ .fno = gen_helper_gvec_##NAME##0_b, \
.fniv = gen_##NAME##0_vec, \
.opt_opc = vecop_list_cmp, \
.vece = MO_8 }, \
{ .fno = gen_helper_gvec_##NAME##0_h, \
.fniv = gen_##NAME##0_vec, \
.opt_opc = vecop_list_cmp, \
.vece = MO_16 }, \
{ .fni4 = gen_##NAME##0_i32, \
.fniv = gen_##NAME##0_vec, \
.opt_opc = vecop_list_cmp, \
.vece = MO_32 }, \
{ .fni8 = gen_##NAME##0_i64, \
.fniv = gen_##NAME##0_vec, \
.opt_opc = vecop_list_cmp, \
.prefer_i64 = TCG_TARGET_REG_BITS == 64, \
.vece = MO_64 }, \
}; \
tcg_gen_gvec_2(d, m, opr_sz, max_sz, &op[vece]); \
}

static const TCGOpcode vecop_list_cmp[] = {
INDEX_op_cmp_vec, 0
};

const GVecGen2 ceq0_op[4] = {
{ .fno = gen_helper_gvec_ceq0_b,
.fniv = gen_ceq0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_8 },
{ .fno = gen_helper_gvec_ceq0_h,
.fniv = gen_ceq0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_16 },
{ .fni4 = gen_ceq0_i32,
.fniv = gen_ceq0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_32 },
{ .fni8 = gen_ceq0_i64,
.fniv = gen_ceq0_vec,
.opt_opc = vecop_list_cmp,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};

static void gen_cle0_i32(TCGv_i32 d, TCGv_i32 a)
{
tcg_gen_setcondi_i32(TCG_COND_LE, d, a, 0);
tcg_gen_neg_i32(d, d);
}

static void gen_cle0_i64(TCGv_i64 d, TCGv_i64 a)
{
tcg_gen_setcondi_i64(TCG_COND_LE, d, a, 0);
tcg_gen_neg_i64(d, d);
}

static void gen_cle0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
{
TCGv_vec zero = tcg_const_zeros_vec_matching(d);
tcg_gen_cmp_vec(TCG_COND_LE, vece, d, a, zero);
tcg_temp_free_vec(zero);
}

const GVecGen2 cle0_op[4] = {
{ .fno = gen_helper_gvec_cle0_b,
.fniv = gen_cle0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_8 },
{ .fno = gen_helper_gvec_cle0_h,
.fniv = gen_cle0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_16 },
{ .fni4 = gen_cle0_i32,
.fniv = gen_cle0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_32 },
{ .fni8 = gen_cle0_i64,
.fniv = gen_cle0_vec,
.opt_opc = vecop_list_cmp,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};

static void gen_cge0_i32(TCGv_i32 d, TCGv_i32 a)
{
tcg_gen_setcondi_i32(TCG_COND_GE, d, a, 0);
tcg_gen_neg_i32(d, d);
}

static void gen_cge0_i64(TCGv_i64 d, TCGv_i64 a)
{
tcg_gen_setcondi_i64(TCG_COND_GE, d, a, 0);
tcg_gen_neg_i64(d, d);
}

static void gen_cge0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
{
TCGv_vec zero = tcg_const_zeros_vec_matching(d);
tcg_gen_cmp_vec(TCG_COND_GE, vece, d, a, zero);
tcg_temp_free_vec(zero);
}

const GVecGen2 cge0_op[4] = {
{ .fno = gen_helper_gvec_cge0_b,
.fniv = gen_cge0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_8 },
{ .fno = gen_helper_gvec_cge0_h,
.fniv = gen_cge0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_16 },
{ .fni4 = gen_cge0_i32,
.fniv = gen_cge0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_32 },
{ .fni8 = gen_cge0_i64,
.fniv = gen_cge0_vec,
.opt_opc = vecop_list_cmp,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};

static void gen_clt0_i32(TCGv_i32 d, TCGv_i32 a)
{
tcg_gen_setcondi_i32(TCG_COND_LT, d, a, 0);
tcg_gen_neg_i32(d, d);
}

static void gen_clt0_i64(TCGv_i64 d, TCGv_i64 a)
{
tcg_gen_setcondi_i64(TCG_COND_LT, d, a, 0);
tcg_gen_neg_i64(d, d);
}

static void gen_clt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
{
TCGv_vec zero = tcg_const_zeros_vec_matching(d);
tcg_gen_cmp_vec(TCG_COND_LT, vece, d, a, zero);
tcg_temp_free_vec(zero);
}

const GVecGen2 clt0_op[4] = {
{ .fno = gen_helper_gvec_clt0_b,
.fniv = gen_clt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_8 },
{ .fno = gen_helper_gvec_clt0_h,
.fniv = gen_clt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_16 },
{ .fni4 = gen_clt0_i32,
.fniv = gen_clt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_32 },
{ .fni8 = gen_clt0_i64,
.fniv = gen_clt0_vec,
.opt_opc = vecop_list_cmp,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};

static void gen_cgt0_i32(TCGv_i32 d, TCGv_i32 a)
{
tcg_gen_setcondi_i32(TCG_COND_GT, d, a, 0);
tcg_gen_neg_i32(d, d);
}

static void gen_cgt0_i64(TCGv_i64 d, TCGv_i64 a)
{
tcg_gen_setcondi_i64(TCG_COND_GT, d, a, 0);
tcg_gen_neg_i64(d, d);
}

static void gen_cgt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a)
{
TCGv_vec zero = tcg_const_zeros_vec_matching(d);
tcg_gen_cmp_vec(TCG_COND_GT, vece, d, a, zero);
tcg_temp_free_vec(zero);
}
GEN_CMP0(ceq, TCG_COND_EQ)
GEN_CMP0(cle, TCG_COND_LE)
GEN_CMP0(cge, TCG_COND_GE)
GEN_CMP0(clt, TCG_COND_LT)
GEN_CMP0(cgt, TCG_COND_GT)

const GVecGen2 cgt0_op[4] = {
{ .fno = gen_helper_gvec_cgt0_b,
.fniv = gen_cgt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_8 },
{ .fno = gen_helper_gvec_cgt0_h,
.fniv = gen_cgt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_16 },
{ .fni4 = gen_cgt0_i32,
.fniv = gen_cgt0_vec,
.opt_opc = vecop_list_cmp,
.vece = MO_32 },
{ .fni8 = gen_cgt0_i64,
.fniv = gen_cgt0_vec,
.opt_opc = vecop_list_cmp,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
#undef GEN_CMP0

static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
{
Expand Down Expand Up @@ -6772,24 +6627,19 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;

case NEON_2RM_VCEQ0:
tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
vec_size, &ceq0_op[size]);
gen_gvec_ceq0(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;
case NEON_2RM_VCGT0:
tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
vec_size, &cgt0_op[size]);
gen_gvec_cgt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;
case NEON_2RM_VCLE0:
tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
vec_size, &cle0_op[size]);
gen_gvec_cle0(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;
case NEON_2RM_VCGE0:
tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
vec_size, &cge0_op[size]);
gen_gvec_cge0(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;
case NEON_2RM_VCLT0:
tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size,
vec_size, &clt0_op[size]);
gen_gvec_clt0(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;

default:
Expand Down
16 changes: 11 additions & 5 deletions target/arm/translate.h
View file
Expand Up @@ -275,11 +275,17 @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
uint64_t vfp_expand_imm(int size, uint8_t imm8);

/* Vector operations shared between ARM and AArch64. */
extern const GVecGen2 ceq0_op[4];
extern const GVecGen2 clt0_op[4];
extern const GVecGen2 cgt0_op[4];
extern const GVecGen2 cle0_op[4];
extern const GVecGen2 cge0_op[4];
void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);

extern const GVecGen3 mla_op[4];
extern const GVecGen3 mls_op[4];
extern const GVecGen3 cmtst_op[4];
Expand Down

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